Jim Grosbach
a428f4ce70
ARM64: [su]xtw use W regs as inputs, not X regs.
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Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing
mode handling.
PR19455 and rdar://16650642
llvm-svn: 206495
2014-04-17 20:47:31 +00:00
Tim Northover
2fa51b50b7
AArch64/ARM64: only mangle MOVZ/MOVN during encoding when needed
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Sometimes we need emit the bits that would actually be a MOVN when producing a
relocated MOVZ instruction (don't ask). But not always, a check which ARM64 got
wrong until now.
llvm-svn: 206289
2014-04-15 14:00:15 +00:00
Stepan Dyatkovskiy
733dd42b91
Optional hash symbol feature support for ARM64
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http://reviews.llvm.org/D3328
llvm-svn: 206276
2014-04-15 11:43:09 +00:00
Alp Toker
111bd28e59
Fix some doc and comment typos
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llvm-svn: 205899
2014-04-09 14:47:27 +00:00
Bradley Smith
9253af77f9
[ARM64] Properly support both apple and standard syntax for FMOV
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llvm-svn: 205896
2014-04-09 14:44:49 +00:00
Bradley Smith
b0ff0afe88
[ARM64] Conditional branches must always print their condition code, even AL.
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llvm-svn: 205894
2014-04-09 14:44:39 +00:00
Bradley Smith
7002e863ee
[ARM64] Add missing shifted register MVN alias to ORN
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llvm-svn: 205891
2014-04-09 14:44:26 +00:00
Bradley Smith
ce010e57ab
[ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types
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llvm-svn: 205888
2014-04-09 14:44:12 +00:00
Bradley Smith
6fa2739377
[ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions.
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llvm-svn: 205886
2014-04-09 14:44:03 +00:00
Bradley Smith
c33112b3a6
[ARM64] Rename LR to the UAL-compliant 'X30'.
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llvm-svn: 205885
2014-04-09 14:43:59 +00:00
Bradley Smith
8923d46955
[ARM64] Rename FP to the UAL-compliant 'X29'.
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llvm-svn: 205884
2014-04-09 14:43:50 +00:00
Bradley Smith
1828a1cae0
[ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu.
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llvm-svn: 205878
2014-04-09 14:43:20 +00:00
Bradley Smith
5b9ef7909e
[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.
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llvm-svn: 205876
2014-04-09 14:43:11 +00:00
Bradley Smith
92cc212005
[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.
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llvm-svn: 205875
2014-04-09 14:43:06 +00:00
Bradley Smith
c795ca6141
[ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.
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llvm-svn: 205871
2014-04-09 14:42:49 +00:00
Bradley Smith
e1a3984e57
[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.
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llvm-svn: 205868
2014-04-09 14:42:36 +00:00
Bradley Smith
1414cc8e91
[ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL)
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llvm-svn: 205864
2014-04-09 14:42:07 +00:00
Bradley Smith
736d891c7c
[ARM64] Add missing 1Q -> 1q vector kind alias
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llvm-svn: 205863
2014-04-09 14:42:01 +00:00
Bradley Smith
731e82da35
[ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}
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llvm-svn: 205862
2014-04-09 14:41:58 +00:00
Bradley Smith
7dde0bc1bc
[ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX
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llvm-svn: 205861
2014-04-09 14:41:53 +00:00
Tim Northover
2f13163a84
ARM64: initial backend import
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This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.
Everything will be easier with the target in-tree though, hence this
commit.
llvm-svn: 205090
2014-03-29 10:18:08 +00:00
