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Commit Graph

142663 Commits

Author SHA1 Message Date
Simon Pilgrim
d6d9c67239 [SLPVectorizer] Regenerate test.
Missed var name

llvm-svn: 290970
2017-01-04 16:01:55 +00:00
Simon Pilgrim
456638db77 Regenerate test.
llvm-svn: 290969
2017-01-04 15:52:41 +00:00
Asiri Rathnayake
0866c9cbc8 Fix x86 gold tests on non-x86 targets.
These tests are missing a target triple and the -m elf_x86_64 gold option,
which makes them fail on non-x86 targets.

Differential revision: https://reviews.llvm.org/D28285

Reviewers: tejohnson
llvm-svn: 290965
2017-01-04 14:43:51 +00:00
Teresa Johnson
6f31c4d0cc [ThinLTO] Rework llvm-link to use the FunctionImporter
Summary:
Change llvm-link to use the FunctionImporter handling, instead of
manually invoking the Linker. We still need to load the module
in llvm-link to do the desired testing for invalid import requests
(weak functions), and to get the GUID (in case the function is local).

Also change the drop-debug-info test to use llvm-link so that importing
is forced (in order to test debug info handling) and independent of
import logic changes.

Reviewers: mehdi_amini

Subscribers: mgorny, llvm-commits, aprantl

Differential Revision: https://reviews.llvm.org/D28277

llvm-svn: 290964
2017-01-04 14:27:31 +00:00
Davide Italiano
a5e403c745 [SPARC] Fix test so that it checks the correct label.
Before it wasn't checking anything.

llvm-svn: 290963
2017-01-04 14:01:58 +00:00
Simon Pilgrim
f1fa399ee0 [CostModel][X86] Updated vXi8 and vXi16 Reverse/Alternate shuffle costs
Actual codegen is much better than the extract+insert patterns that was assumed.

llvm-svn: 290962
2017-01-04 14:01:33 +00:00
Nemanja Ivanovic
3b5ff305e9 [PowerPC] Add identification for POWER8NVL
This CPU type was not previously recognized by LLVM which led to emitting
poor (and sometimes incorrect) code in some JIT workloads on such a machine.

llvm-svn: 290961
2017-01-04 13:58:09 +00:00
Davide Italiano
19898f9d33 [MC/COFF] Fix a test to actually check the relocation.
Inspired by r290953 + grep -R 'CHCEK'.

llvm-svn: 290958
2017-01-04 13:12:00 +00:00
Simon Pilgrim
2f667f5eca [X86] Merged Reverse/Alternate shuffle cost tables. NFCI.
As discussed on D27811, merged the shuffle cost LUTs and use the shuffle kind to perform the lookup instead of the ISD opcode.

llvm-svn: 290956
2017-01-04 12:08:41 +00:00
Florian Hahn
9f0b7fd455 [framelowering] Skip dbg values when getting next/previous instruction.
Summary:
In mergeSPUpdates, debug values need to be ignored when getting the
previous element, otherwise debug data could have an impact on codegen.

In eliminateCallFramePseudoInstr, debug values after the erased element
could have an impact on codegen and should be skipped.

Closes PR31319 (https://llvm.org/bugs/show_bug.cgi?id=31319)

Reviewers: aprantl, MatzeB, mkuper

Subscribers: gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D27688

llvm-svn: 290955
2017-01-04 12:08:35 +00:00
Chandler Carruth
d541339c25 [ADT] Speculative attempt to fix build bot issues with r290952.
This just removes the usage of llvm::reverse and llvm::seq. That makes
it harder to handle the empty case correctly and so I've also added
a test there.

This is just a shot in the dark at what might be behind the buildbot
failures. I can't reproduce any issues locally including with ASan...
I feel like I'm missing something...

llvm-svn: 290954
2017-01-04 11:40:18 +00:00
Chandler Carruth
3afacf4c6f [Inliner] Fix a test where I typo'ed 'CHECK' as 'CHCEK' when converting
to FileCheck.

Fortunately, it passes. =]

Spotted in review by Bob Wilson!

llvm-svn: 290953
2017-01-04 11:15:01 +00:00
Chandler Carruth
5c979966df [ADT] Enhance the PriorityWorklist to support bulk insertion.
This is both convenient and more efficient as we can skip any
intermediate reallocation of the vector.

This usage pattern came up in a subsequent patch on the pass manager,
but it seems generically useful so I factored it out and added unittests
here.

llvm-svn: 290952
2017-01-04 11:13:11 +00:00
Bjorn Pettersson
53828bbf87 Fix for InlineSpiller accessing not updated dom tree base information.
Summary:
The InlineSpiller was accessing the DominatorTreeBase directly
through the public data member DT in the MachineDominatorTree.
This is not a good idea as the "cached" information in
SplitCriticalEdges is not applied before the access.
The DominatorTreeBase must be accessed through the member
function getBase() in MachineDominatorTree.

The fault was introduced in r266162.

I think the public data member DT in the MachineDominatorTree
should have been made private in the original code (r215576)
that introduced the concept of lazily updating the
MachineDominatorTree information from
MachineBasicBlock::SplitCriticalEdge().

Patch by Karl-Johan Karlsson <karl-johan.karlsson@ericsson.com>

Reviewers: wmi, qcolombet

Subscribers: llvm-commits, bjope, uabelho

Differential Revision: https://reviews.llvm.org/D27983

llvm-svn: 290950
2017-01-04 09:41:56 +00:00
Nitesh Jain
6eba6db512 [LLC][MIPS] Fix crash after enabling LLVM_ENABLE_EXPENSIVE_CHECKS
Reviewers: sdardis, vkalintiris

Subscribers: jaydeep, slthakur, RKSimon, llvm-commits
Differential Revision: https://reviews.llvm.org/D27841

llvm-svn: 290949
2017-01-04 09:34:37 +00:00
Ayman Musa
3f2cc3457f [X86][AVX512] Passing the appropriate memory operand class to INT_{U}COMIS{S|D} instructions
Replacing the memory operand in the intrinsic versions of the comis/ucomis instrucions from f128mem to ssmem/sdmem accordingly.

Differential Revision: https://reviews.llvm.org/D28138

llvm-svn: 290948
2017-01-04 08:21:54 +00:00
Simon Pilgrim
31a63f3400 [X86] Attempt to pre-truncate arithmetic operations if useful
In some cases its more efficient to combine TRUNC( BINOP( X, Y ) ) --> BINOP( TRUNC( X ), TRUNC( Y ) ) if the binop is legal for the truncated types.

This is true for vector integer multiplication (especially vXi64), as well as ADD/AND/XOR/OR in cases where we only need to truncate one of the inputs at runtime (e.g. a duplicated input or an one use constant we can fold).

Further work could be done here - scalar cases (especially i64) could often benefit (if we avoid partial registers etc.), other opcodes, and better analysis of when truncating the inputs reduces costs.

I have considered implementing this for all targets within the DAGCombiner but wasn't sure we could devise a suitable cost model system that would give us the range we need.

Differential Revision: https://reviews.llvm.org/D28219

llvm-svn: 290947
2017-01-04 08:05:42 +00:00
Craig Topper
92d154bbfd [AVX-512] Add support for detecting 512-bit shuffles that contain a 128-bit subvector insertion from the lowest subvector of one of the sources.
These are best handled with a vinsert32x4 or vinsert64x2 instruction.

llvm-svn: 290946
2017-01-04 07:32:03 +00:00
Craig Topper
302240f3f0 [AVX-512] Add more test cases for shuffles that should be handled with subvector insert instructions.
llvm-svn: 290945
2017-01-04 07:31:59 +00:00
Craig Topper
b059ce31fb [AVX-512] Fix a typo in a couple case names to match their behavior.
llvm-svn: 290944
2017-01-04 07:31:57 +00:00
Craig Topper
e1e80531cc [AVX-512] Add avx512dq to the vector-shuffle-512-v16.ll test command lines in preparation for a future change that needs these features.
llvm-svn: 290943
2017-01-04 07:31:54 +00:00
Craig Topper
4d9daa9fee [AVX-512] Simplify code for creating 512-bit SHUF128 operations.
We don't need two loops and we can safely assume assume and hardcode the size of the widened mask.

llvm-svn: 290942
2017-01-04 07:31:51 +00:00
Peter Collingbourne
590787f185 Support: Add YAML I/O support for custom mappings.
This will be used to YAMLify parts of the module summary.

Differential Revision: https://reviews.llvm.org/D28014

llvm-svn: 290935
2017-01-04 03:51:36 +00:00
Eric Christopher
eccfa8e3a4 On a 64-bit system, the DWARFDebugLine::Row struct is 32 bytes. Each field has the following byte offsets:
0-7: Address
8-11: Line
12-13: Column
14-15: File
16-19: Isa
20-23: Discriminator
24+: bit fields

The packing is fine until the "Isa" field, which is an 8-bit int that occupies 4 bytes. We can instead move Discriminator into the 16-19 slot, and pack Isa into the 20-23 range along with the bit fields:

0-7: Address
8-11: Line
12-13: Column
14-15: File
16-19: Discriminator
20-23: Isa + bit fields

This layout is only 24 bytes. This 25% reduction in size may seem small but a large binary can have line tables with thousands of rows stored in a vector.

Patch by Simon Que!

Differential Revision: https://reviews.llvm.org/D27961

llvm-svn: 290931
2017-01-04 02:34:29 +00:00
David Majnemer
eaee470355 [InstCombine] Add a test for r290733
llvm-svn: 290929
2017-01-04 02:21:37 +00:00
David Majnemer
1199f6c23b [InstCombine] Move casts around shift operations
It is possible to perform a left shift before zero extending if the
shift would only shift out zeros.

llvm-svn: 290928
2017-01-04 02:21:34 +00:00
David Majnemer
01104cb956 [InstCombine] Combine adds across a zext
We can perform the following:
(add (zext (add nuw X, C1)), C2) -> (zext (add nuw X, C1+C2))

This is only possible if C2 is negative and C2 is greater than or equal to negative C1.

llvm-svn: 290927
2017-01-04 02:21:31 +00:00
Eugene Zelenko
c4c44537b4 [Hexagon, TableGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 290925
2017-01-04 02:02:05 +00:00
Greg Clayton
fd505c31d7 Correct the parent testing to avoid the special case where a DIE has a depth of 1
This test was testing that we could correctly find the parent of a DIE, but it was actually just testing the special case where a DIE's depth was 1. This corrects that error by adding an extra level into the the DWARF to ensure that we correctly get the parent by looking for the parent with a depth that is 1 less than the current depth.

Differential Revision: https://reviews.llvm.org/D28261

llvm-svn: 290918
2017-01-04 00:10:50 +00:00
Teresa Johnson
22248b4bd6 [ThinLTO] Import type as decl only when non-null Identifier
As per post-commit review for r289993 (D27775), we can only safely
import a type as a decl if it has an Identifier, as the Name alone
is not enough to be unique across modules.

llvm-svn: 290915
2017-01-03 23:19:29 +00:00
Zachary Turner
2a893b4054 Fix the MSVC version check.
I'm not sure what determines the minor version, but it appears
that it's possible for a fully updated, release version of
VS2015 with Update 3 can go (at least) as low as 19.00.24213.1.
Updating the compiler version check to account for this so we
don't generate superfluous warnings.

llvm-svn: 290914
2017-01-03 23:12:36 +00:00
Matt Arsenault
9fca19b426 InstCombine: Fold fabs on select of constants
llvm-svn: 290913
2017-01-03 22:40:34 +00:00
Sanjay Patel
571db5f912 [InstCombine] use 'match' to reduce code bloat; NFCI
I wrote this patch before seeing the comment in:
https://reviews.llvm.org/D27114
...that suggests we should actually be canonicalizing the other way.

So just in case we decide this is the right way, we might as well
have a cleaner implementation.

llvm-svn: 290912
2017-01-03 22:25:31 +00:00
Ahmed Bougacha
af2642b0e5 [CodeGen] Further simplify returned call operand logic. NFC.
As Pete points out in r290905, CallSite lets us avoid duplicating this!

llvm-svn: 290909
2017-01-03 21:42:43 +00:00
Lang Hames
a2f7ccec83 [ExecutionEngine] Fix compile errors in OProfileJITEventListener.
Allows LLVM to build with LLVM_USE_OPROFILE=True.

Patch by Mark Dewing. Thanks Mark!

llvm-svn: 290908
2017-01-03 21:39:43 +00:00
Ahmed Bougacha
9258c02aa0 [CodeGen] Simplify logic that looks for returned call operands. NFC-ish.
Use getReturnedArgOperand() instead of rolling our own.  Note that it's
equivalent because there can only be one 'returned' operand.

The existing code was also incorrect: there already was awkward logic to
ignore callee/EH blocks, but operands can now also be operand bundles,
in which case we'll look for non-existent parameter attributes.

Unfortunately, this isn't observable in-tree, as it only crashes when
exercising the regular call lowering logic with operand bundles.
Still, this is a nice small cleanup anyway.

llvm-svn: 290905
2017-01-03 20:33:22 +00:00
Sanjay Patel
0428428089 [InstCombine] tighten checks for tests of assume -> metadata transform; NFC
llvm-svn: 290903
2017-01-03 19:32:11 +00:00
Simon Pilgrim
20defba2af [X86][SSE] Add extra truncated arithmetic tests for D28219
llvm-svn: 290902
2017-01-03 19:18:07 +00:00
Adrian Prantl
b86fd9630b Add llvm-bcanalyzer support for new metadata node types.
Also sort the existing list by value.

llvm-svn: 290901
2017-01-03 19:17:49 +00:00
Xin Tong
810b2dcdb6 Enable disabled loopidiom test. Apparently we handle it now
Summary:
Enable disabled loopidiom test. Apparently we handle it now.
Maybe due to improvements to AA.

Reviewers: atrick, danielcdh, hfinkel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D28171

llvm-svn: 290900
2017-01-03 19:08:05 +00:00
Kostya Serebryany
2e864a9222 [libFuzzer] disable -print_pcs by default (was enabled by mistake)
llvm-svn: 290899
2017-01-03 18:51:28 +00:00
Michal Gorny
7f8c085cf4 [ADT] APFloatBase: Prevent collapsing semPPCDoubleDouble and semBogus
Provide a distinct contents for semBogus and semPPCDoubleDouble in order
to prevent compilers from collapsing them to a single memory address,
while we heavily rely on every semantic having distinct address.

This happens if insecure optimization collapsing identical values is
enabled. As a result, APFloats of semBogus are indistinguishable from
semPPCDoubleDouble -- and whenever the move constructor is used, the old
value beings being incorrectly recognized as a semPPCDoubleDouble.

Since the values in semPPCDoubleDouble are not used anywhere,
we can easily solve this issue via altering the value of one of the
fields and therefore ensuring that the collapse can not occur.

Differential Revision: https://reviews.llvm.org/D28112

llvm-svn: 290896
2017-01-03 16:33:50 +00:00
Craig Topper
1249148650 [X86] Move 128-bit shuffle mask widening check into lowerV2X128VectorShuffle to reduce code duplication. Use the now available widened mask to simplify some code inside lowerV2X128VectorShuffle.
llvm-svn: 290872
2017-01-03 07:36:41 +00:00
Craig Topper
1714188cbd [AVX-512] Simplify the code added in r290870 to recognized 256-bit subvector inserts and avoid calling isShuffleEquivalent on a widened mask.
llvm-svn: 290871
2017-01-03 07:36:39 +00:00
Craig Topper
835037106b [AVX-512] Teach shuffle lowering to use vinsert instructions for shuffles corresponding to 256-bit subvector inserts.
llvm-svn: 290870
2017-01-03 07:00:40 +00:00
Craig Topper
0b239e015a [AVX-512] Teach EVEX to VEX conversion pass to handle VINSERT and VEXTRACT instructions.
llvm-svn: 290869
2017-01-03 05:46:18 +00:00
Craig Topper
bc487cedf4 [AVX-512] Re-generate tests that were updated for r290663 without using update_llc_test_checks.py so duplicate check lines weren't merged.
llvm-svn: 290868
2017-01-03 05:46:10 +00:00
Craig Topper
347c84f468 [X86] Remove trailing whitespace and an unnecessary line wrap. NFC
llvm-svn: 290867
2017-01-03 05:46:06 +00:00
Craig Topper
e5417c03a6 [X86] Fix header comment. NFC
llvm-svn: 290866
2017-01-03 05:46:05 +00:00
Craig Topper
6cd1971371 [AVX-512] Add support for pushing bitcasts through INSERT_SUBVEC in order to select a masked operation.
llvm-svn: 290865
2017-01-03 05:46:02 +00:00