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Commit Graph

92193 Commits

Author SHA1 Message Date
David Majnemer
d705d7cb59 [CodeView] Include the offset of nested members
Given something like:
  struct S {
    int a;
    struct { int b; };
  };

We would fail to give 'b' offset 4.  Instead, we would give it the
offset it has inside of it's struct.

llvm-svn: 274400
2016-07-01 23:12:48 +00:00
David Majnemer
0ef767bae6 [CodeView] Pretty print anonymous scopes
A namespace without a name should be written out as `anonymous
namespace' while a tag type without a name should be written out as
<unnamed-tag>.

llvm-svn: 274399
2016-07-01 23:12:45 +00:00
Matt Arsenault
164529a800 AMDGPU: Add feature for unaligned access
llvm-svn: 274398
2016-07-01 23:03:44 +00:00
Matt Arsenault
fcc3666c3b AMDGPU: Expand unaligned accesses early
Due to visit order problems, in the case of an unaligned copy
the legalized DAG fails to eliminate extra instructions introduced
by the expansion of both unaligned parts.

llvm-svn: 274397
2016-07-01 22:55:55 +00:00
Evgeniy Stepanov
782843c112 [msan] Fix __msan_maybe_ for non-standard type sizes.
Fix incorrect calculation of the type size for __msan_maybe_warning_N
call that resulted in an invalid (narrowing) zext instruction and
"Assertion `castIsValid(op, S, Ty) && "Invalid cast!"' failed."

Only happens in very large functions (with more than 3500 MSan
checks) operating on integer types that are not power-of-two.

llvm-svn: 274395
2016-07-01 22:49:59 +00:00
Matt Arsenault
14dbe93675 AMDGPU: Improve load/store of illegal types.
There was a combine before to handle the simple copy case.
Split this into handling loads and stores separately.

We might want to change how this handles some of the vector
extloads, since this can result in large code size increases.

llvm-svn: 274394
2016-07-01 22:47:50 +00:00
Reid Kleckner
d61604b293 [codeview] Don't record UDTs for anonymous structs
MSVC makes up names for these anonymous structs, but we don't (yet).
Eventually Clang should use getTypedefNameForAnonDecl() to put some name
in the debug info, and we can update the test case when that happens.

llvm-svn: 274391
2016-07-01 22:24:51 +00:00
Alina Sbirlea
a67b649a17 Address two correctness issues in LoadStoreVectorizer
Summary:
GetBoundryInstruction returns the last instruction as the instruction which follows or end(). Otherwise the last instruction in the boundry set is not being tested by isVectorizable().
Partially solve reordering of instructions. More extensive solution to follow.

Reviewers: tstellarAMD, llvm-commits, jlebar

Subscribers: escha, arsenm, mzolotukhin

Differential Revision: http://reviews.llvm.org/D21934

llvm-svn: 274389
2016-07-01 21:44:12 +00:00
Krzysztof Parzyszek
018aee0772 [Hexagon] Revert r274381: that was actually wrong
llvm-svn: 274384
2016-07-01 20:45:19 +00:00
Krzysztof Parzyszek
3e2e7ad563 [Hexagon] Use MachineOperand::readsReg instead of isUse
llvm-svn: 274381
2016-07-01 20:28:30 +00:00
Reid Kleckner
c2f9ee812a [pdb] Check the display name for <unnamed-tag>, not the linkage name
This issue was encountered on libcmt.pdb, which has a type record that
looks like this:

  Struct (0x1094) {
    TypeLeafKind: LF_STRUCTURE (0x1505)
    MemberCount: 3
    Properties [ (0x200)
      HasUniqueName (0x200)
    ]
    FieldList: <field list> (0x1093)
    DerivedFrom: 0x0
    VShape: 0x0
    SizeOf: 4
    Name: <unnamed-tag>
    LinkageName: .?AU<unnamed-tag>@@
  }

The checks for startswith/endswith "<unnamed-tag>" should look at the
display name, not the linkage name.

llvm-svn: 274376
2016-07-01 18:43:29 +00:00
Reid Kleckner
b9e92cdeb3 [codeview] Assert that our CV type records are valid
We were asserting that our type records were valid when emitting
assembly, but not when emitting an object file.

I've been seeing lots of LNK1285 errors (corrupt PDB) during incremental
debug self-host builds with the MSVC linker, and hopefully this will
catch some of them earlier.

llvm-svn: 274373
2016-07-01 18:05:56 +00:00
Matt Arsenault
792d48b8f4 AMDGPU/SI: Enable testing several variants for si scheduler
Enable testing different scheduling variants if sgpr usage
is very high. It was previously disabled because of a bug
in handleMove, but it has been fixed since.

Patch by Axel Davy

llvm-svn: 274372
2016-07-01 18:03:46 +00:00
Hans Wennborg
dea5b2087b Revert r274347 "[ARM] Refactor Thumb2 mul instruction descs"
This caused PR28387: Assertion "#operands for dag node doesn't match .td file!"

llvm-svn: 274367
2016-07-01 17:26:42 +00:00
Duncan P. N. Exon Smith
73e9436c33 CodeGen: Use MachineInstr& in RegisterCoalescer, NFC
Remove a few more implicit iterator to pointer conversions by preferring
MachineInstr&.

llvm-svn: 274363
2016-07-01 16:43:13 +00:00
Sanjay Patel
e0079e069e fix documentation comments; NFC
llvm-svn: 274362
2016-07-01 16:41:59 +00:00
Duncan P. N. Exon Smith
33cfbe6ec5 CodeGen: Avoid implicit conversions in TargetInstrInfo, NFC
Avoid implicit conversions from MachineBasicBlock::iterator to
MachineInstr* in TargetInstrInfo.

llvm-svn: 274361
2016-07-01 16:38:28 +00:00
Duncan P. N. Exon Smith
e18b83f903 CodeGen: Use MachineInstr& in ScheduleDAGIntrs, NFC
Use MachineInstr& to avoid implicit conversions from
MachineBasicBlock::iterator to MachineInstr*.  In one case, this could
use a range-based for loop, but the other loops iterated in reverse
order.

One of the reverse-loops checked the MachineInstr* for nullptr, a
condition that is provably unreachable.  (And even if my proof has a
flaw, UBSan would catch the bug.)

llvm-svn: 274360
2016-07-01 16:21:48 +00:00
Dehao Chen
3cbfdf1355 Do not count debug instructions when counting number of uses to reorder frame objects.
Summary: The code generation should be independent of the debug info.

Reviewers: zansari, davidxl, mkuper, majnemer

Subscribers: majnemer, llvm-commits

Differential Revision: http://reviews.llvm.org/D21911

llvm-svn: 274357
2016-07-01 15:40:25 +00:00
Duncan P. N. Exon Smith
30f3e96e65 CodeGen: Avoid iterator conversion in UnreachableBlockElim, NFC
Avoid an unnecessary (and implicit) iterator to pointer conversion in
UnreachableBlockElim by using the post-increment operator.

llvm-svn: 274355
2016-07-01 15:13:09 +00:00
Duncan P. N. Exon Smith
5553404c2b CodeGen: Use MachineInstr& in SlotIndexes.cpp, NFC
Avoid implicit conversions from iterator to pointer by preferring
MachineInstr& and using range-based for loops.

llvm-svn: 274354
2016-07-01 15:08:52 +00:00
Duncan P. N. Exon Smith
51fdaa6f97 CodeGen: Use MachineInstr& in RegAllocFast, NFC
Use MachineInstr& instead of MachineInstr* in RegAllocFast to avoid
implicit conversions from MachineInstrBundleIterator.  RAFast::spillAll
and RAFast::spillVirtReg still take iterators, since their argument may
be an end iterator from MachineBasicBlock::getFirstTerminator.

llvm-svn: 274353
2016-07-01 15:03:37 +00:00
Sam Parker
9afffaa0dd [ARM] Refactor Thumb2 mul instruction descs
No functional changes. Just created wrapper classes around the 3
and 4 reg mult and mac instruction classes.

Differential Revision: http://reviews.llvm.org/D21549

llvm-svn: 274347
2016-07-01 12:55:49 +00:00
Benjamin Kramer
a8509b51f9 function_refify. NFC.
While there use emplace_back to create an expensive pair.

llvm-svn: 274344
2016-07-01 11:05:15 +00:00
Nikolay Haustov
2290e3d147 Resubmit r268719 - AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2.
This was reverted in r268740 because of problems with corresponding Clang change.
Clang change was updated and resubmitted in r274220.

Check calling convention in AMDGPUMachineFunction::isKernel

This will be used for AMDGPU_HSA_KERNEL symbol type in output ELF.

Also, in the future unused non-kernels may be optimized.

Reviewers: tstellarAMD, arsenm

Subscribers: arsenm, joker.eph, llvm-commits

Differential Revision: http://reviews.llvm.org/D19917

llvm-svn: 274341
2016-07-01 10:00:58 +00:00
Sam Kolton
f50ff4ead4 [AMDGPU] Assembler: support SDWA for VOPC instructions
Summary: dst_sel and dst_unused disabled for VOPC as they have no effect on result

Reviewers: artem.tamazov, tstellarAMD, vpykhtin

Subscribers: arsenm, kzhuravl

Differential Revision: http://reviews.llvm.org/D21376

llvm-svn: 274340
2016-07-01 09:59:21 +00:00
NAKAMURA Takumi
1b4696ec50 Update libdeps; AMDGPUCodeGen requires LLVMVectorize.
llvm-svn: 274339
2016-07-01 09:55:23 +00:00
Craig Topper
139f298043 [CodeGen] Cleanup getVectorShuffle a bit to take advantage of its new ArrayRef argument and its begin/end iterators. Also use 'int' type for number of elements and loop iterators to remove several typecasts. No functional change intended.
llvm-svn: 274338
2016-07-01 06:54:51 +00:00
Craig Topper
0caa8a6b4a [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a pointer to a mask array. Convert all callers to use the ArrayRef version. No functional change intended.
For the most part this simplifies all callers. There were two places in X86 that needed an explicit makeArrayRef to shorten a statically sized array.

llvm-svn: 274337
2016-07-01 06:54:47 +00:00
Eric Christopher
6a7de5ae52 Add support for allowing us to create uniquely identified "COMDAT" or "ELF
Group" sections while lowering. In particular, for ELF sections this is
useful for creating function-specific groups that get merged into the
same named section.

Also use const Twine& instead of StringRef for the getELF functions
while we're here.

Differential Revision: http://reviews.llvm.org/D21743

llvm-svn: 274336
2016-07-01 06:07:38 +00:00
Eric Christopher
bd2c7c3f2d 80-column and comment fixups.
llvm-svn: 274335
2016-07-01 06:07:31 +00:00
Xinliang David Li
11bf9401be [PM] refactor LoopAccessInfo code part-2
Differential Revision: http://reviews.llvm.org/D21636

llvm-svn: 274334
2016-07-01 05:59:55 +00:00
Xinliang David Li
159144914d [MBP] method interface cleanup
Make worklist and ehworklist member of the
class so that they don't need to be passed around.

llvm-svn: 274333
2016-07-01 05:46:48 +00:00
Matt Arsenault
f430ee2504 AMDGPU: Add option to run the load/store vectorizer
llvm-svn: 274329
2016-07-01 03:33:52 +00:00
Reid Kleckner
f448343ea4 [codeview] Add DISubprogram::ThisAdjustment
Summary:
This represents the adjustment applied to the implicit 'this' parameter
in the prologue of a virtual method in the MS C++ ABI. The adjustment is
always zero unless multiple inheritance is involved.

This increases the size of DISubprogram by 8 bytes, unfortunately. The
adjustment really is a signed 32-bit integer. If this size increase is
too much, we could probably win it back by splitting out a subclass with
info specific to virtual methods (virtuality, vindex, thisadjustment,
containingType).

Reviewers: aprantl, dexonsmith

Subscribers: aaboud, amccarth, llvm-commits

Differential Revision: http://reviews.llvm.org/D21614

llvm-svn: 274325
2016-07-01 02:41:21 +00:00
Matt Arsenault
8fd475f7bc LoadStoreVectorizer: improvements: better pointer analysis
If OpB has an ADD NSW/NUW, we can use that to prove that adding 1
to OpA won't wrap if OpA + 1 == OpB.

Patch by Fiona Glaser

llvm-svn: 274324
2016-07-01 02:16:24 +00:00
Matt Arsenault
672f531e85 LoadStoreVectorizer: Don't increase alignment with no align set
If no alignment was set on the load/stores, it would vectorize
to the new type even though this increases the default alignment.

llvm-svn: 274323
2016-07-01 02:09:38 +00:00
Matt Arsenault
4d99aca7bd LoadStoreVectorizer: Check TTI for vec reg bit width
llvm-svn: 274322
2016-07-01 02:07:22 +00:00
Matt Arsenault
94a201efeb LoadStoreVectorizer: Fix assert when merging pointer ops
This needs to use inttoptr/ptrtoint if combining an int and pointer
load. If a pointer is used always do an integer load.

llvm-svn: 274321
2016-07-01 01:55:52 +00:00
Duncan P. N. Exon Smith
ffdaac761a Revert "code hoisting pass based on GVN"
This reverts commit r274305, since it breaks self-hosting:
  http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_build/22349/
  http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules/builds/17232

Note that the blamelist on lab.llvm.org:8011 is incorrect.  The previous
build was r274299, but somehow r274305 wasn't included in the blamelist:
  http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules

llvm-svn: 274320
2016-07-01 01:51:40 +00:00
Duncan P. N. Exon Smith
00a6a7099d CodeGen: Use MachineInstr& in LiveVariables API, NFC
Change all the methods in LiveVariables that expect non-null
MachineInstr* to take MachineInstr& and update the call sites.  This
clarifies the API, and designs away a class of iterator to pointer
implicit conversions.

llvm-svn: 274319
2016-07-01 01:51:32 +00:00
Matt Arsenault
1386cebc2f LoadStoreVectorizer: Use AA metadata
This was not passing the full instruction with metadata
to the alias query.

llvm-svn: 274318
2016-07-01 01:47:46 +00:00
Duncan P. N. Exon Smith
1dc5b6903f CodeGen: Remove implicit iterator conversions in PHIElimination, NFC
llvm-svn: 274317
2016-07-01 01:27:19 +00:00
Duncan P. N. Exon Smith
b3e43a0ae5 CodeGen: Use MachineInstr& in PostRASchedulerList, NFC
Remove another unnecessary iterator to pointer conversion.

llvm-svn: 274315
2016-07-01 01:18:53 +00:00
Matt Arsenault
e8398c9c3e AMDGPU: Implement getLoadStoreVecRegBitWidth
llvm-svn: 274312
2016-07-01 00:56:27 +00:00
Duncan P. N. Exon Smith
0a44b07c9f CodeGen: Use MachineInstr& in PostRAHazardRecognizer, NFC
Convert a loop to a range-based for, using MachineInstr& instead of
MachineInstr* and removing an implicit conversion from iterator to
pointer.

llvm-svn: 274311
2016-07-01 00:50:29 +00:00
Duncan P. N. Exon Smith
d414c8259f CodeGen: Use MachineInstr& in PrologEpilogInserter, NFC
Use MachineInstr& over MachineInstr* to avoid implicit iterator to
pointer conversions.  MachineInstr*-as-nullptr was being used as a flag
for whether the for loop terminated normally; I added an explicit `bool`
instead.

llvm-svn: 274310
2016-07-01 00:40:57 +00:00
Reid Kleckner
1e8c103f99 [pdb] Avoid reporting an error when the module symbol stream is empty
llvm-svn: 274309
2016-07-01 00:37:49 +00:00
Reid Kleckner
a8e16f1432 [PDB] Indicate which type record failed hash validation
llvm-svn: 274308
2016-07-01 00:37:25 +00:00
Matt Arsenault
1b62244124 LoadStoreVectorizer: if one element of a vector is integer, default to
integer.

Fixes issues on some architectures where we use arithmetic ops to build
vectors, which can cause bad things to happen for loads/stores of mixed
types.

Patch by Fiona Glaser

llvm-svn: 274307
2016-07-01 00:37:01 +00:00