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Author SHA1 Message Date
Chris Lattner
e5344b1169 Physregs may hold multiple stack slot values at the same time. Keep track 
of this, and use it to our advantage (bwahahah).  This allows us to eliminate another
60 instructions from smg2000 on PPC (probably significantly more on X86).  A common
old-new diff looks like this:

        stw r2, 3304(r1)
-       lwz r2, 3192(r1)
        stw r2, 3300(r1)
-       lwz r2, 3192(r1)
        stw r2, 3296(r1)
-       lwz r2, 3192(r1)
        stw r2, 3200(r1)
-       lwz r2, 3192(r1)
        stw r2, 3196(r1)
-       lwz r2, 3192(r1)
+       or r2, r2, r2
        stw r2, 3188(r1)

and

-       lwz r31, 604(r1)
-       lwz r13, 604(r1)
-       lwz r14, 604(r1)
-       lwz r15, 604(r1)
-       lwz r16, 604(r1)
-       lwz r30, 604(r1)
+       or r31, r30, r30
+       or r13, r30, r30
+       or r14, r30, r30
+       or r15, r30, r30
+       or r16, r30, r30
+       or r30, r30, r30

Removal of the R = R copies is coming next...

llvm-svn: 25919
 2006-02-03 00:36:31 +00:00
Chris Lattner
66d0341e73 update a note 
llvm-svn: 25918
 2006-02-02 23:50:22 +00:00
Chris Lattner
935255c984 Fix a deficiency in the spiller that Evan noticed. In particular, consider 
this code:

  store [stack slot #0],  R10
    = add R14, [stack slot #0]

The spiller didn't know that the store made the value of [stackslot#0] available
in R10 *IF* the store came from a copy instruction with the store folded into it.

This patch teaches VirtRegMap to look at these stores and recognize the values
they make available.  In one case Evan provided, this code:

        divsd %XMM0, %XMM1
        movsd %XMM1, QWORD PTR [%ESP + 40]
1)      movsd QWORD PTR [%ESP + 48], %XMM1
2)      movsd %XMM1, QWORD PTR [%ESP + 48]
        addsd %XMM1, %XMM0
3)      movsd QWORD PTR [%ESP + 48], %XMM1
        movsd QWORD PTR [%ESP + 4], %XMM0

turns into:

        divsd %XMM0, %XMM1
        movsd %XMM1, QWORD PTR [%ESP + 40]
        addsd %XMM1, %XMM0
3)      movsd QWORD PTR [%ESP + 48], %XMM1
        movsd QWORD PTR [%ESP + 4], %XMM0

In this case, instruction #2 was removed because of the value made
available by #1, and inst #1 was later deleted because it is now
never used before the stack slot is redefined by #3.

This occurs here and there in a lot of code with high spilling, on PPC
most of the removed loads/stores are LSU-reject-causing loads, which is
nice.

On X86, things are much better (because it spills more), where we nuke
about 1% of the instructions from SMG2000 and several hundred from eon.

More improvements to come...

llvm-svn: 25917
 2006-02-02 23:29:36 +00:00
Nate Begeman
09bdfffaa6 add 64b gpr store to the possible list of isStoreToStackSlot opcodes. 
llvm-svn: 25916
 2006-02-02 21:07:50 +00:00
Chris Lattner
452b75a57b fix operand numbers 
llvm-svn: 25915
 2006-02-02 20:38:12 +00:00
Chris Lattner
8337a1050d implement isStoreToStackSlot for PPC 
llvm-svn: 25914
 2006-02-02 20:16:12 +00:00
Chris Lattner
15cb732cd7 Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) 
llvm-svn: 25913
 2006-02-02 20:12:32 +00:00
Chris Lattner
10f9a9daa5 implement isStoreToStackSlot 
llvm-svn: 25911
 2006-02-02 20:00:41 +00:00
Chris Lattner
876bbd4faa add a method 
llvm-svn: 25910
 2006-02-02 19:57:16 +00:00
Chris Lattner
ebf20d47ac more notes 
llvm-svn: 25908
 2006-02-02 19:43:28 +00:00
Chris Lattner
8a8c101989 add a note, I have no idea how important this is. 
llvm-svn: 25907
 2006-02-02 19:16:34 +00:00
Chris Lattner
95fe9f5df2 %fcc is not an alias for %fcc0 
llvm-svn: 25906
 2006-02-02 08:02:20 +00:00
Chris Lattner
f5c935f882 correct an opcode 
llvm-svn: 25905
 2006-02-02 07:56:15 +00:00
Chris Lattner
c434ee61a3 new example 
llvm-svn: 25903
 2006-02-02 07:37:11 +00:00
Nate Begeman
dd4acf9710 Update the README 
llvm-svn: 25902
 2006-02-02 07:27:56 +00:00
Chris Lattner
456711ae45 Turn any_extend nodes into zero_extend nodes when it allows us to remove an 
and instruction.  This allows us to compile stuff like this:

bool %X(int %X) {
        %Y = add int %X, 14
        %Z = setne int %Y, 12345
        ret bool %Z
}

to this:

_X:
        cmpl $12331, 4(%esp)
        setne %al
        movzbl %al, %eax
        ret

instead of this:

_X:
        cmpl $12331, 4(%esp)
        setne %al
        movzbl %al, %eax
        andl $1, %eax
        ret

This occurs quite a bit with the X86 backend.  For example, 25 times in
lambda, 30 times in 177.mesa, 14 times in galgel,  70 times in fma3d,
25 times in vpr, several hundred times in gcc, ~45 times in crafty,
~60 times in parser, ~140 times in eon, 110 times in perlbmk, 55 on gap,
16 times on bzip2, 14 times on twolf, and 1-2 times in many other SPEC2K
programs.

llvm-svn: 25901
 2006-02-02 07:17:31 +00:00
Chris Lattner
c2ec404142 Implement MaskedValueIsZero for ANY_EXTEND nodes 
llvm-svn: 25900
 2006-02-02 06:43:15 +00:00
Chris Lattner
32762f6c01 implemented, testcase here: test/Regression/CodeGen/X86/compare-add.ll 
llvm-svn: 25899
 2006-02-02 06:36:48 +00:00
Chris Lattner
8f4d73f3da add two dag combines: 
(C1-X) == C2 --> X == C1-C2
(X+C1) == C2 --> X == C2-C1

This allows us to compile this:

bool %X(int %X) {
        %Y = add int %X, 14
        %Z = setne int %Y, 12345
        ret bool %Z
}

into this:

_X:
        cmpl $12331, 4(%esp)
        setne %al
        movzbl %al, %eax
        andl $1, %eax
        ret

not this:

_X:
        movl $14, %eax
        addl 4(%esp), %eax
        cmpl $12345, %eax
        setne %al
        movzbl %al, %eax
        andl $1, %eax
        ret

Testcase here: Regression/CodeGen/X86/compare-add.ll

nukage of the and coming up next.

llvm-svn: 25898
 2006-02-02 06:36:13 +00:00
Evan Cheng
94b1244255 Update. 
llvm-svn: 25896
 2006-02-02 02:40:17 +00:00
Chris Lattner
f3bfec6117 make -debug output less newliney 
llvm-svn: 25895
 2006-02-02 00:38:08 +00:00
Evan Cheng
d432c17927 Fix a erroneous comment. 
llvm-svn: 25894
 2006-02-02 00:28:23 +00:00
Chris Lattner
e35694c0bf Implement matching constraints. We can now say things like this: 
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)

and get:

xyz r2, r3, r4, r2

note that the r2's are pinned together.  Yaay for 2-address instructions.

2342 ----------------------------------------------------------------------

llvm-svn: 25893
 2006-02-02 00:25:23 +00:00
Chris Lattner
a8429e5f11 validate matching constraints and remember when we see them. 
llvm-svn: 25892
 2006-02-02 00:23:53 +00:00
Chris Lattner
26451058cb more notes 
llvm-svn: 25890
 2006-02-01 23:38:08 +00:00
Evan Cheng
8c988b64ae Tell codegen MOVAPSrr and MOVAPDrr are copies. 
llvm-svn: 25889
 2006-02-01 23:03:16 +00:00
Evan Cheng
adc4966129 Added SSE entries to foldMemoryOperand(). 
llvm-svn: 25888
 2006-02-01 23:02:25 +00:00
Evan Cheng
b78bb375c2 Rearrange code to my liking. :) 
llvm-svn: 25887
 2006-02-01 23:01:57 +00:00
Chris Lattner
41a35db65f Implement smart printing of inline asm strings, handling variants and 
substituted operands.  For this testcase:

int %test(int %A, int %B) {
  %C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
  ret int %C
}

we now emit:

_test:
        or r2, r3, r3
        or r3, r4, r4
        xyz r2, r2, r3  ;; look here
        or r3, r2, r2
        blr

... note the substituted operands. :)

llvm-svn: 25886
 2006-02-01 22:41:11 +00:00
Chris Lattner
d202c4d3cc add a method 
llvm-svn: 25884
 2006-02-01 22:38:46 +00:00
Chris Lattner
8004ba8a2b another note 
llvm-svn: 25883
 2006-02-01 21:44:48 +00:00
Andrew Lenharth
9812806d03 Add immediate forms of cmov and remove some cruft 
llvm-svn: 25882
 2006-02-01 19:37:33 +00:00
Nate Begeman
e74a2db0f0 *** empty log message *** 
llvm-svn: 25879
 2006-02-01 19:05:15 +00:00
Chris Lattner
9665c2d76f Implement simple register assignment for inline asms. This allows us to compile: 
int %test(int %A, int %B) {
  %C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
  ret int %C
}

into:

 (0x8906130, LLVM BB @0x8902220):
        %r2 = OR4 %r3, %r3
        %r3 = OR4 %r4, %r4
        INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
        %r3 = OR4 %r2, %r2
        BLR

which asmprints as:

_test:
        or r2, r3, r3
        or r3, r4, r4
        xyz $0, $1, $2      ;; need to print the operands now :)
        or r3, r2, r2
        blr

llvm-svn: 25878
 2006-02-01 18:59:47 +00:00
Chris Lattner
4042f63422 Finegrainify namespacification 
llvm-svn: 25877
 2006-02-01 18:10:56 +00:00
Chris Lattner
821f93a659 add a note 
llvm-svn: 25876
 2006-02-01 17:54:23 +00:00
Nate Begeman
0be60963bd Fix some of the stuff in the PPC README file, and clean up legalization 
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.

llvm-svn: 25875
 2006-02-01 07:19:44 +00:00
Chris Lattner
d2fb7bf108 add a note, I'll take care of this after nate commits his big patch 
llvm-svn: 25873
 2006-02-01 06:40:32 +00:00
Evan Cheng
ef93bdc0cf - Use xor to clear integer registers (set R, 0). 
- Added a new format for instructions where the source register is implied
  and it is same as the destination register. Used for pseudo instructions
  that clear the destination register.

llvm-svn: 25872
 2006-02-01 06:13:50 +00:00
Evan Cheng
6523b2de76 Remove another entry. 
llvm-svn: 25871
 2006-02-01 06:08:48 +00:00
Jeff Cohen
8b429890aa Fix VC++ compilation error. 
llvm-svn: 25869
 2006-02-01 04:37:04 +00:00
Chris Lattner
0e7d439232 Another regression from the pattern isel 
llvm-svn: 25867
 2006-02-01 01:44:25 +00:00
Chris Lattner
fa15301572 Beef up the interface to inline asm constraint parsing, making it more general, useful, and easier to use. 
llvm-svn: 25866
 2006-02-01 01:29:47 +00:00
Chris Lattner
5549a10792 adjust to changes in InlineAsm interface. Fix a few minor bugs. 
llvm-svn: 25865
 2006-02-01 01:28:23 +00:00
Evan Cheng
27738f635e Return's chain should be matching either the chain produced by the 
value or the chain going into the load.

llvm-svn: 25863
 2006-02-01 01:19:32 +00:00
Chris Lattner
c270dd87a9 another testcase. 
llvm-svn: 25862
 2006-02-01 00:28:12 +00:00
Evan Cheng
329e86ddfa When folding a load into a return of SSE value, check the chain to 
ensure the memory location has not been clobbered.

llvm-svn: 25861
 2006-02-01 00:20:21 +00:00
Evan Cheng
19b80eebb2 Remove an item. It's done. 
llvm-svn: 25860
 2006-02-01 00:15:53 +00:00
Evan Cheng
7eb36f4721 Be smarter about whether to store the SSE return value in memory. If 
it is already available in memory, do a fld directly from there.

llvm-svn: 25859
 2006-01-31 23:19:54 +00:00
Chris Lattner
bb410d0b63 turning these into 'adds' would require extra copies 
llvm-svn: 25858
 2006-01-31 22:59:46 +00:00
Evan Cheng
45ebd632f2 - Allow XMM load (for scalar use) to be folded into ANDP* and XORP*. 
- Use XORP* to implement fneg.

llvm-svn: 25857
 2006-01-31 22:28:30 +00:00
Evan Cheng
6d9aae44f9 Remove entries on fabs and fneg. These are done. 
llvm-svn: 25856
 2006-01-31 22:26:21 +00:00
Evan Cheng
f115c17f23 Allow the specification of explicit alignments for constant pool entries. 
llvm-svn: 25855
 2006-01-31 22:23:14 +00:00
Chris Lattner
5587b270e4 * Fix 80-column violations 
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.

llvm-svn: 25854
 2006-01-31 19:43:35 +00:00
Chris Lattner
892fe31362 add info about the inline asm register constraints for PPC 
llvm-svn: 25853
 2006-01-31 19:20:21 +00:00
Evan Cheng
80944be4e7 Allow custom lowering of fabs. I forgot to check in this change which 
caused several test failures.

llvm-svn: 25852
 2006-01-31 18:14:25 +00:00
Chris Lattner
b54e4baa26 add a missing break that caused a lot of failures last night :( 
llvm-svn: 25851
 2006-01-31 17:20:06 +00:00
Nate Begeman
7a83bb4285 Codegen 
bool %test(int %X) {
  %Y = seteq int %X, 13
  ret bool %Y
}

as

_test:
        addi r2, r3, -13
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

rather than

_test:
        cmpwi cr7, r3, 13
        mfcr r2
        rlwinm r3, r2, 31, 31, 31
        blr

This has very little effect on most code, but speeds up analyzer 23% and
mason 11%

llvm-svn: 25848
 2006-01-31 08:17:29 +00:00
Chris Lattner
798747b798 okay, one more 
llvm-svn: 25847
 2006-01-31 07:45:45 +00:00
Chris Lattner
c831039792 another note 
llvm-svn: 25846
 2006-01-31 07:45:08 +00:00
Chris Lattner
5d718dbc1e More notes 
llvm-svn: 25845
 2006-01-31 07:43:33 +00:00
Chris Lattner
e0d5ccdecf another one 
llvm-svn: 25844
 2006-01-31 07:38:32 +00:00
Chris Lattner
66751830ed add a note 
llvm-svn: 25843
 2006-01-31 07:37:20 +00:00
Chris Lattner
1a0bf14366 add conditional moves of float and double values on int/fp condition codes. 
llvm-svn: 25842
 2006-01-31 07:26:55 +00:00
Chris Lattner
186b5f0887 example nate pointed out 
llvm-svn: 25841
 2006-01-31 07:16:34 +00:00
Chris Lattner
769e683663 treat conditional branches the same way as conditional moves (giving them 
an operand that contains the condcode), making things significantly simpler.

llvm-svn: 25840
 2006-01-31 06:56:30 +00:00
Chris Lattner
a999c688d5 compactify all of the integer conditional moves into one instruction that takes 
a CC as an operand.  Much smaller, much happier.

llvm-svn: 25839
 2006-01-31 06:49:09 +00:00
Chris Lattner
5aade7535c Add immediate forms of integer cmovs 
llvm-svn: 25838
 2006-01-31 06:24:29 +00:00
Chris Lattner
c1b80cb2fe Shrinkify 
llvm-svn: 25837
 2006-01-31 06:18:16 +00:00
Chris Lattner
fcd00875a9 Add the full complement of conditional moves of integer registers. 
llvm-svn: 25834
 2006-01-31 05:26:36 +00:00
Chris Lattner
9d29548015 Compile this: 
void %X(int %A) {
        %C = setlt int %A, 123          ; <bool> [#uses=1]
        br bool %C, label %T, label %F

T:              ; preds = %0
        call int %main( int 0 )         ; <int>:0 [#uses=0]
        ret void

F:              ; preds = %0
        ret void
}

to this:

X:
        save -96, %o6, %o6
        subcc %i0, 122, %l0
        bg .LBBX_2      ! F
        nop
...

not this:

X:
        save -96, %o6, %o6
        sethi 0, %l0
        or %g0, 1, %l1
        subcc %i0, 122, %l2
        bg .LBBX_4      !
        nop
.LBBX_3:        !
        or %g0, %l0, %l1
.LBBX_4:        !
        subcc %l1, 0, %l0
        bne .LBBX_2     ! F
        nop

llvm-svn: 25833
 2006-01-31 05:05:52 +00:00
Chris Lattner
d33e8efd56 Only insert an AND when converting from BR_COND to BRCC if needed. 
llvm-svn: 25832
 2006-01-31 05:04:52 +00:00
Evan Cheng
49467b6b5b Added custom lowering of fabs 
llvm-svn: 25831
 2006-01-31 03:14:29 +00:00
Chris Lattner
830b1ad8cf add the 'lucas' optimization 
llvm-svn: 25830
 2006-01-31 02:55:28 +00:00
Chris Lattner
213a7b78fb I don't see why this optimization isn't safe, but it isn't, so disable it 
llvm-svn: 25829
 2006-01-31 02:45:52 +00:00
Chris Lattner
9b89cad951 Another high-prio selection performance bug 
llvm-svn: 25828
 2006-01-31 02:10:06 +00:00
Chris Lattner
e113238f5c Handle physreg input/outputs. We now compile this: 
int %test_cpuid(int %op) {
        %B = alloca int
        %C = alloca int
        %D = alloca int
        %A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
        %Bv = load int* %B
        %Cv = load int* %C
        %Dv = load int* %D
        %x = add int %A, %Bv
        %y = add int %x, %Cv
        %z = add int %y, %Dv
        ret int %z
}

to this:

_test_cpuid:
        sub %ESP, 16
        mov DWORD PTR [%ESP], %EBX
        mov %EAX, DWORD PTR [%ESP + 20]
        cpuid
        mov DWORD PTR [%ESP + 8], %ECX
        mov DWORD PTR [%ESP + 12], %EBX
        mov DWORD PTR [%ESP + 4], %EDX
        mov %ECX, DWORD PTR [%ESP + 12]
        add %EAX, %ECX
        mov %ECX, DWORD PTR [%ESP + 8]
        add %EAX, %ECX
        mov %ECX, DWORD PTR [%ESP + 4]
        add %EAX, %ECX
        mov %EBX, DWORD PTR [%ESP]
        add %ESP, 16
        ret

... note the proper register allocation.  :)

it is unclear to me why the loads aren't folded into the adds.

llvm-svn: 25827
 2006-01-31 02:03:41 +00:00
Chris Lattner
899754747c more mumbling 
llvm-svn: 25826
 2006-01-31 00:45:37 +00:00
Chris Lattner
76a85bd047 add some notes 
llvm-svn: 25825
 2006-01-31 00:20:38 +00:00
Evan Cheng
38aacb5f09 Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip 
the order of the compare operands and generate SETOGT, SETOGE, SETUGE, and
SETULE instead.

llvm-svn: 25824
 2006-01-30 23:41:35 +00:00
Chris Lattner
ce37ba3417 Print the most trivial inline asms. 
llvm-svn: 25822
 2006-01-30 23:00:08 +00:00
Chris Lattner
e24c6ef1f9 Fix a bug in my legalizer reworking that caused the X86 backend to not get 
a chance to custom legalize setcc, which broke a bunch of C++ Codes.
Testcase here: CodeGen/X86/2006-01-30-LongSetcc.ll

llvm-svn: 25821
 2006-01-30 22:43:50 +00:00
Chris Lattner
3ae06dac75 Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure from last night 
llvm-svn: 25819
 2006-01-30 22:20:49 +00:00
Evan Cheng
8ea651a9a4 i64 -> f32, f32 -> i64 and some clean up. 
llvm-svn: 25818
 2006-01-30 22:13:22 +00:00
Evan Cheng
d2d96373dc Always use FP stack instructions to perform i64 to f64 as well as f64 to i64 
conversions. SSE does not have instructions to handle these tasks.

llvm-svn: 25817
 2006-01-30 08:02:57 +00:00
Chris Lattner
baa47e9a6e Revamp the ICC/FCC reading instructions to be parameterized in terms of the 
SPARC condition codes, not in terms of the DAG condcodes.  This allows us to
write nice clean patterns for cmovs/branches.

llvm-svn: 25815
 2006-01-30 07:43:04 +00:00
Chris Lattner
7925da8b3b Compile: 
uint %test(uint %X) {
        %Y = call uint %llvm.ctpop.i32(uint %X)
        ret uint %Y
}

to:

test:
        save -96, %o6, %o6
        sll %i0, 0, %l0
        popc %l0, %i0
        restore %g0, %g0, %g0
        retl
        nop

instead of to 40 logical ops.  Note the shift-by-zero that clears the top
part of the 64-bit V9 register.

Testcase here: CodeGen/SparcV8/ctpop.ll

llvm-svn: 25814
 2006-01-30 06:14:02 +00:00
Chris Lattner
0c7df7e9d1 If the target has V9 instructions, this pass is a noop, don't bother 
running it.

llvm-svn: 25811
 2006-01-30 05:51:14 +00:00
Chris Lattner
69658ab9a8 When in v9 mode, emit fabsd/fnegd/fmovd 
llvm-svn: 25810
 2006-01-30 05:48:37 +00:00
Chris Lattner
98667e5f6a First step towards V9 instructions in the V8 backend, two conditional move 
patterns.  This allows emission of this code:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        move %icc, %i0, %i2
        or %g0, %i2, %i0
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        be .LBBt1_2     !
        nop
.LBBt1_1:       !
        or %g0, %i2, %i0
.LBBt1_2:       !
        restore %g0, %g0, %g0
        retl
        nop

for this:

int %t1(int %a, int %b, int %c) {
        %tmp.2 = seteq int %a, %b
        %tmp3 = select bool %tmp.2, int %a, int %c
        ret int %tmp3
}

llvm-svn: 25809
 2006-01-30 05:35:57 +00:00
Chris Lattner
8b5958a832 Two changes: 
1. Default to having V9 instructions, instead of just V8.
2. unless -enable-sparc-v9-insts is passed, disable V9 (for use with llcbeta)

llvm-svn: 25807
 2006-01-30 04:57:43 +00:00
Chris Lattner
f0ea60bc01 When lowering SELECT_CC, see if the input is a lowered SETCC. If so, fold 
the two operations together.  This allows us to compile this:

void %two(int %a, int* %b) {
        %tmp.2 = seteq int %a, 0
        %tmp.0.0 = select bool %tmp.2, int 10, int 20
        store int %tmp.0.0, int* %b
        ret void
}

into:

two:
        save -96, %o6, %o6
        or %g0, 20, %l0
        or %g0, 10, %l1
        subcc %i0, 0, %l2
        be .LBBtwo_2    ! entry
        nop
.LBBtwo_1:      ! entry
        or %g0, %l0, %l1
.LBBtwo_2:      ! entry
        st %l1, [%i1]
        restore %g0, %g0, %g0
        retl
        nop

instead of:

two:
        save -96, %o6, %o6
        sethi 0, %l0
        or %g0, 1, %l1
        or %g0, 20, %l2
        or %g0, 10, %l3
        subcc %i0, 0, %l4
        be .LBBtwo_2    ! entry
        nop
.LBBtwo_1:      ! entry
        or %g0, %l0, %l1
.LBBtwo_2:      ! entry
        subcc %l1, 0, %l0
        bne .LBBtwo_4   ! entry
        nop
.LBBtwo_3:      ! entry
        or %g0, %l2, %l3
.LBBtwo_4:      ! entry
        st %l3, [%i1]
        restore %g0, %g0, %g0
        retl
        nop

llvm-svn: 25806
 2006-01-30 04:34:44 +00:00
Jeff Cohen
d80b0d7375 Add AddSymbol() method to DynamicLibrary to work around Windows limitation 
of being unable to search for symbols in an EXE.  It will also allow other
existing hacks to be improved.

llvm-svn: 25805
 2006-01-30 04:33:51 +00:00
Chris Lattner
4ba0e38a7a don't insert an and node if it isn't needed here, this can prevent folding 
of lowered target nodes.

llvm-svn: 25804
 2006-01-30 04:22:28 +00:00
Chris Lattner
a44182300b Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. 
llvm-svn: 25803
 2006-01-30 04:09:27 +00:00
Chris Lattner
354340b1b1 Implement isMaskedValueZeroForTargetNode for the various v8 selectcc nodes, 
allowing redundant and's to be eliminated by the dag combiner.

llvm-svn: 25800
 2006-01-30 03:51:45 +00:00
Chris Lattner
26589d32e6 pass the address of MaskedValueIsZero into isMaskedValueZeroForTargetNode, 
to permit recursion

llvm-svn: 25799
 2006-01-30 03:49:37 +00:00
Chris Lattner
754bc1f46c adjust prototype 
llvm-svn: 25798
 2006-01-30 03:49:07 +00:00
Jeff Cohen
f8d118706f Fix indentation. 
llvm-svn: 25795
 2006-01-29 22:02:52 +00:00
Chris Lattner
414a73d6f6 Fix RET of promoted values on targets that custom expand RET to a target node. 
llvm-svn: 25794
 2006-01-29 21:02:23 +00:00
Chris Lattner
2ab7f21d20 Functions that are lazily streamed in from the .bc file are *not* external. 
This fixes llvm-test/SingleSource/UnitTests/2006-01-29-SimpleIndirectCall.c
and PR704

llvm-svn: 25793
 2006-01-29 20:49:17 +00:00
Chris Lattner
9bb580ac23 add another note 
llvm-svn: 25789
 2006-01-29 09:46:06 +00:00
Chris Lattner
7ec490d6d6 add some performance notes from looking at sgefa 
llvm-svn: 25788
 2006-01-29 09:42:20 +00:00
Chris Lattner
7a775bff1e add a high-priority SSE issue from sgefa 
llvm-svn: 25787
 2006-01-29 09:14:47 +00:00
Chris Lattner
7048df99cd add a missed optimization 
llvm-svn: 25786
 2006-01-29 09:08:15 +00:00
Chris Lattner
497157db4d cleanups to the ValueTypeActions interface 
llvm-svn: 25785
 2006-01-29 08:42:06 +00:00
Chris Lattner
4c6384a412 Now that OpActions is big enough, we can specify actions for vector types 
llvm-svn: 25784
 2006-01-29 08:41:37 +00:00
Chris Lattner
81edad23a6 clean up interface to ValueTypeActions 
llvm-svn: 25783
 2006-01-29 08:41:12 +00:00
Chris Lattner
3cddcf86e0 Remove some special case hacks for CALLSEQ_*, using UpdateNodeOperands 
instead.

llvm-svn: 25780
 2006-01-29 07:58:15 +00:00
Chris Lattner
00e9ba5526 disable this for now 
llvm-svn: 25778
 2006-01-29 07:31:33 +00:00
Reid Spencer
2669d4cb81 Add a note about lowering llvm.memset, llvm.memcpy, and llvm.memmove to a 
few stores under certain conditions.

llvm-svn: 25777
 2006-01-29 06:48:25 +00:00
Chris Lattner
73262d78b8 remove now-dead code, the legalizer takes care of this for us 
llvm-svn: 25776
 2006-01-29 06:45:31 +00:00
Chris Lattner
b66484069a The FP stack doesn't support UNDEF, ask the legalizer to legalize it 
instead of lying and saying we have it.

llvm-svn: 25775
 2006-01-29 06:44:22 +00:00
Chris Lattner
94e9677374 Allow custom expansion of ConstantVec nodes. PPC will use this in the future. 
llvm-svn: 25774
 2006-01-29 06:34:16 +00:00
Chris Lattner
6c4173145e Request expansion of ConstantVec nodes. 
llvm-svn: 25773
 2006-01-29 06:32:58 +00:00
Chris Lattner
3f97b9cfa3 Legalize ConstantFP into TargetConstantFP when the target allows. Implement 
custom expansion of ConstantFP nodes.

llvm-svn: 25772
 2006-01-29 06:26:56 +00:00
Chris Lattner
5f0a3df176 Targets all now request ConstantFP to be legalized into TargetConstantFP. 
'fpimm' in .td files is now TargetConstantFP.

llvm-svn: 25771
 2006-01-29 06:26:08 +00:00
Chris Lattner
ca5c2d7a4c Update alpha to reflect recent constantfp legalize changes. It's not clear 
why all this code isn't autogenerated. :(

llvm-svn: 25770
 2006-01-29 06:25:22 +00:00
Chris Lattner
82b23c2f5c eliminate uses of SelectionDAG::getBR2Way_CC 
llvm-svn: 25767
 2006-01-29 06:00:45 +00:00
Chris Lattner
7a06abe72b cmovle != cmovlt 
llvm-svn: 25761
 2006-01-29 03:47:30 +00:00
Jeff Cohen
28a7bd94c9 Fix typo. 
llvm-svn: 25760
 2006-01-29 03:45:35 +00:00
Jeff Cohen
3ef56b005a Flesh out AMD family/models. 
llvm-svn: 25755
 2006-01-28 20:30:18 +00:00
Jeff Cohen
08656fa2a6 Correctly determine CPU vendor. 
llvm-svn: 25754
 2006-01-28 19:48:34 +00:00
Jeff Cohen
057816014c Use union instead of reinterpret_cast. 
llvm-svn: 25751
 2006-01-28 18:47:32 +00:00
Jeff Cohen
6d330738c1 Fix recognition of Intel CPUs. 
llvm-svn: 25750
 2006-01-28 18:38:20 +00:00
Chris Lattner
e5bf55bf7b Is64Bit reflects the capability of the chip, not an aspect of the target os 
llvm-svn: 25749
 2006-01-28 18:23:48 +00:00
Chris Lattner
0256ca3257 Fix a bunch of JIT failures with the new isel 
llvm-svn: 25748
 2006-01-28 18:19:37 +00:00
Jeff Cohen
4d971bdfa7 Improve X86 subtarget support for Windows and AMD. 
llvm-svn: 25747
 2006-01-28 18:09:06 +00:00
Chris Lattner
40973347bf Use the new "UpdateNodeOperands" method to simplify LegalizeDAG and make it 
faster.  This cuts about 120 lines of code out of the legalizer (mostly code
checking to see if operands have changed).

It also fixes an ugly performance issue, where the legalizer cloned the entire
graph after any change.  Now the "UpdateNodeOperands" method gives it a chance
to reuse nodes if the operands of a node change but not its opcode or valuetypes.

This speeds up instruction selection time on kimwitu++ by about 8.2% with a
release build.

llvm-svn: 25746
 2006-01-28 10:58:55 +00:00
Chris Lattner
744d9a40f0 silence a warning 
llvm-svn: 25745
 2006-01-28 10:34:47 +00:00
Chris Lattner
8768eb7532 add another method variant 
llvm-svn: 25744
 2006-01-28 10:09:25 +00:00
Chris Lattner
63f7e84632 add some methods for updating nodes 
llvm-svn: 25742
 2006-01-28 09:32:45 +00:00
Chris Lattner
99bdf26410 minor tweaks 
llvm-svn: 25740
 2006-01-28 08:31:04 +00:00
Chris Lattner
94ab3cee71 move a bunch of code, no other change. 
llvm-svn: 25739
 2006-01-28 08:25:58 +00:00
Chris Lattner
9633d61b5b remove a couple more now-extraneous legalizeop's 
llvm-svn: 25738
 2006-01-28 08:22:56 +00:00
Chris Lattner
4bc3abc3d0 fix a bug 
llvm-svn: 25737
 2006-01-28 07:42:08 +00:00
Chris Lattner
8eed1b6bda Several major changes: 
1. Pull out the expand cases for BSWAP and CT* into a separate function,
   reducing the size of LegalizeOp.
2. Fix a bug where expand(bswap i64) was wrong when i64 is legal.
3. Changed LegalizeOp/PromoteOp so that the legalizer never needs to be
   iterative.  It now operates in a single pass over the nodes.
4. Simplify a LOT of code, with a net reduction of ~280 lines.

llvm-svn: 25736
 2006-01-28 07:39:30 +00:00
Chris Lattner
d2eb15f467 Fix a bug in my elimination of ISD::CALL this morning. PPC now has to 
provide the expansion for i64 calls itself

llvm-svn: 25735
 2006-01-28 07:33:03 +00:00
Chris Lattner
686a1203f0 make this work on non-native hosts 
llvm-svn: 25734
 2006-01-28 06:05:41 +00:00
Chris Lattner
170727421b add a note about how we should implement this FIXME from the legalizer: 
// FIXME: revisit this when we have some kind of mechanism by which targets
    // can decided legality of vector constants, of which there may be very
    // many.

llvm-svn: 25733
 2006-01-28 05:40:47 +00:00
Chris Lattner
84086fd689 Eliminate the need for ExpandOp to set 'needsanotheriteration', as it already 
relegalizes the stuff it returns.

Add the ability to custom expand ADD/SUB, so that targets don't need to deal
with ADD_PARTS/SUB_PARTS if they don't want.

Fix some obscure potential bugs and simplify code.

llvm-svn: 25732
 2006-01-28 05:07:51 +00:00
Chris Lattner
3b5a984065 Instead of making callers of ExpandLibCall legalize the result, make 
ExpandLibCall do it itself.

llvm-svn: 25731
 2006-01-28 04:28:26 +00:00
Chris Lattner
045a778e63 Eliminate the need to do another iteration of the legalizer after inserting 
a libcall.

llvm-svn: 25730
 2006-01-28 04:23:12 +00:00
Chris Lattner
d6d4bcc419 remove method I just added 
llvm-svn: 25728
 2006-01-28 03:43:09 +00:00
Chris Lattner
063c13029b add a new callback 
llvm-svn: 25727
 2006-01-28 03:37:03 +00:00
Nate Begeman
87c2c0e66b Implement Promote for VAARG, and allow it to be custom promoted for people 
who don't want the default behavior (Alpha).

llvm-svn: 25726
 2006-01-28 03:14:31 +00:00
Nate Begeman
a46156da35 Add a couple more things to the readme. 
llvm-svn: 25724
 2006-01-28 01:22:10 +00:00
Nate Begeman
dc3fba6b6b Add a missing case to the dag combiner. 
llvm-svn: 25723
 2006-01-28 01:06:30 +00:00
Chris Lattner
e7428f436a Remove the ISD::CALL and ISD::TAILCALL nodes 
llvm-svn: 25721
 2006-01-28 00:18:58 +00:00
Chris Lattner
d467a681e9 Remove some dead code 
llvm-svn: 25719
 2006-01-28 00:02:51 +00:00
Chris Lattner
2d4f83eaaf Switch to AlphaISD::CALL instead of ISD::CALL 
llvm-svn: 25718
 2006-01-27 23:39:00 +00:00
Chris Lattner
6a5d2450a3 Use PPCISD::CALL instead of ISD::CALL 
llvm-svn: 25717
 2006-01-27 23:34:02 +00:00
Chris Lattner
ab3ad7d4ef Use V8ISD::CALL instead of ISD::CALL 
llvm-svn: 25716
 2006-01-27 23:30:03 +00:00
Evan Cheng
442713efd7 A bit of wisdom from Chris on the last entry. 
llvm-svn: 25715
 2006-01-27 22:54:32 +00:00
Evan Cheng
03aaa82992 AT&T assembly convention: registers are in lower case. 
llvm-svn: 25714
 2006-01-27 22:53:29 +00:00
Chris Lattner
c245c32022 initialize member vars 
llvm-svn: 25712
 2006-01-27 22:38:36 +00:00
Chris Lattner
35d325e8aa initialize all instance vars 
llvm-svn: 25711
 2006-01-27 22:37:09 +00:00
Chris Lattner
59a4f3f637 Make llvm.frame/returnaddr not crash on ppc 
llvm-svn: 25710
 2006-01-27 22:25:06 +00:00
Evan Cheng
51c1d32061 Added notes about a x86 isel deficiency. 
llvm-svn: 25706
 2006-01-27 22:11:01 +00:00
Evan Cheng
5c1d0d40dc Added a temporary option -enable-x86-sse to enable sse support. It is used by 
llc-beta.

llvm-svn: 25701
 2006-01-27 21:49:34 +00:00
Evan Cheng
746086dc97 Bye bye Pattern ISel, hello DAG ISel. 
llvm-svn: 25700
 2006-01-27 21:26:54 +00:00
Nate Begeman
d2c6fbef4a Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for 
the same functionality.  This addresses another piece of bug 680.  Next,
on to fixing Alpha VAARG, which I broke last time.

llvm-svn: 25696
 2006-01-27 21:09:22 +00:00
Jim Laskey
c8759505c4 Using bit size of integers instead of ambiguous "long" et all. 
llvm-svn: 25694
 2006-01-27 20:31:25 +00:00
Evan Cheng
577ea086c4 A better workaround 
llvm-svn: 25692
 2006-01-27 19:30:30 +00:00
Jim Laskey
2221ac79d5 Sorry - really folowing convention. 
llvm-svn: 25691
 2006-01-27 18:32:41 +00:00
Chris Lattner
932260bb64 force sse/3dnow off until they work. This fixes all the x86 failures last night 
llvm-svn: 25690
 2006-01-27 18:30:50 +00:00
Jim Laskey
479abc37ff Following convention. 
llvm-svn: 25689
 2006-01-27 18:28:31 +00:00
Chris Lattner
e1f4b9e384 Unbreak the JIT with SSE 
llvm-svn: 25688
 2006-01-27 18:27:18 +00:00
Andrew Lenharth
67e53709df fix build 
llvm-svn: 25687
 2006-01-27 18:16:17 +00:00
Chris Lattner
e4128dc8dc Fix build error that is apparently only a warning with some compilers. 
llvm-svn: 25686
 2006-01-27 17:31:30 +00:00
Jim Laskey
5ed7bc82cc Forgot the version number. 
llvm-svn: 25685
 2006-01-27 15:46:54 +00:00
Jim Laskey
89492c12bb Improve visibility/correctness of operand indices in "llvm.db" objects. 
Handle 64 in DIEs.

llvm-svn: 25684
 2006-01-27 15:20:54 +00:00
Reid Spencer
bd79be19a2 Fix auto-upgrade of intrinsics to work properly with both assembly and 
bytecode reading. This code is crufty, the result of much hacking to get things
working correctly. Cleanup patches will follow.

llvm-svn: 25682
 2006-01-27 11:49:27 +00:00
Evan Cheng
5891f49c47 x86 CPU detection and proper subtarget support 
llvm-svn: 25679
 2006-01-27 08:10:46 +00:00
Evan Cheng
77885c204d Subtarget feature can now set any variable to any value 
llvm-svn: 25678
 2006-01-27 08:09:42 +00:00
Chris Lattner
09d8aa244e Stub out a method 
llvm-svn: 25676
 2006-01-27 02:10:10 +00:00
Chris Lattner
20d4194a0d PHI and INLINEASM are now built-in instructions provided by Target.td 
llvm-svn: 25674
 2006-01-27 01:46:15 +00:00
Chris Lattner
8cef15a908 Add a default NoItinerary class for targets to use. 
llvm-svn: 25670
 2006-01-27 01:41:38 +00:00
Chris Lattner
a1769576f0 Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an 
ISD::INLINEASM node.

llvm-svn: 25668
 2006-01-26 23:28:04 +00:00
Chris Lattner
b2771c7fcb initial selectiondag support for new INLINEASM node. Note that inline asms 
with outputs or inputs are not supported yet. :)

llvm-svn: 25664
 2006-01-26 22:24:51 +00:00
Jim Laskey
df47d0df3e Use global information to fill out Dwarf compile units. 
llvm-svn: 25662
 2006-01-26 21:22:49 +00:00
Jeff Cohen
f329a41a66 Improve compatibility with VC2005, patch by Morten Ofstad! 
llvm-svn: 25661
 2006-01-26 20:41:32 +00:00
Chris Lattner
800999ca4b Implement a method for inline asm support 
llvm-svn: 25660
 2006-01-26 20:37:03 +00:00
Jim Laskey
583aae3110 Set up MachineDebugInfo to scan for debug information form "llvm.db"g globals. 
Global Variable information is now pulled from "llvm.dbg.globals"

llvm-svn: 25655
 2006-01-26 20:21:46 +00:00
Chris Lattner
bfd5404cbf Improve compatibility with VC2005, patch by Morten Ofstad! 
llvm-svn: 25653
 2006-01-26 19:55:20 +00:00
Andrew Lenharth
a2054ac660 dynamically allocate plugin space as needed 
llvm-svn: 25652
 2006-01-26 19:38:58 +00:00
Andrew Lenharth
c2973ea159 Remember plugins should someone like bugpoint want to know them. 
llvm-svn: 25649
 2006-01-26 18:36:50 +00:00
Evan Cheng
670dc80530 Added preliminary x86 subtarget support. 
llvm-svn: 25645
 2006-01-26 09:53:06 +00:00
Duraid Madina
f868d1777b fix stack corruption! Previously, 16-byte whole-FP-register stores were 
being treated as needing only 8 bytes (though they were 16 byte aligned.)

This should fix a bunch of tests - anyone have any comments, though?

  - in Target.td , SpillSize and SpillAlignment seem dead - is this what
    Size and Alignment do now?
  - in CodeGenRegisters.h/CodeGenTarget.cpp , DeclaredSpillSize and
    DeclaredSpillAlignment seem dead.
  - there are a bunch of comments here and there that don't clearly
    distinguish between 'size' and 'spillsize' etc. hmm.

llvm-svn: 25644
 2006-01-26 09:45:03 +00:00
Duraid Madina
13335846a8 some hoovering 
llvm-svn: 25643
 2006-01-26 09:08:31 +00:00
Chris Lattner
0204d70798 Rest of subtarget support, remove references to ppc 
llvm-svn: 25642
 2006-01-26 07:22:22 +00:00
Chris Lattner
eb424bfbca Add trivial subtarget support 
llvm-svn: 25641
 2006-01-26 06:51:21 +00:00
Andrew Lenharth
23afe2f288 minor renaming 
llvm-svn: 25640
 2006-01-26 03:24:15 +00:00
Andrew Lenharth
ad88ba7c98 allow R28 to be used for frame calculations without entirely removing it from circulation 
llvm-svn: 25639
 2006-01-26 03:22:07 +00:00
Evan Cheng
7a77e3f80c Work around some x86 Darwin assembler bugs 
llvm-svn: 25638
 2006-01-26 02:27:43 +00:00
Chris Lattner
c88610d074 add method for constraint parsing 
llvm-svn: 25637
 2006-01-26 02:21:59 +00:00
Evan Cheng
bf29b90240 When trying to fold X86::SETCC into a Select, make a copy if it has more than 
one use. This allows more CMOV instructions.

llvm-svn: 25634
 2006-01-26 02:13:10 +00:00
Chris Lattner
66f10c8957 teach the cloner to handle inline asms 
llvm-svn: 25633
 2006-01-26 01:55:22 +00:00
Chris Lattner
a0c517622a parse and verify the constraint string. 
llvm-svn: 25631
 2006-01-26 00:48:33 +00:00
Evan Cheng
fcd2a73349 Clean up some code; improve efficiency; and fixed a potential bug involving 
chain successors.

llvm-svn: 25630
 2006-01-26 00:30:29 +00:00
Evan Cheng
224e14daa1 Remove the uses of STATUS flag register. Rely on node property SDNPInFlag, 
SDNPOutFlag, and SDNPOptInFlag instead.

llvm-svn: 25629
 2006-01-26 00:29:36 +00:00
Chris Lattner
e930f6bafb Make sure the only user of InlineAsm's are direct calls. 
llvm-svn: 25626
 2006-01-26 00:08:45 +00:00
Andrew Lenharth
084c16fe59 oops 
llvm-svn: 25623
 2006-01-25 23:33:32 +00:00
Chris Lattner
db805c3206 add bc reader/writer support for inline asm 
llvm-svn: 25621
 2006-01-25 23:08:15 +00:00
Andrew Lenharth
01e5b9e862 forgot one 
llvm-svn: 25620
 2006-01-25 22:28:07 +00:00
Chris Lattner
a4f17ed13e regenerate 
llvm-svn: 25619
 2006-01-25 22:27:16 +00:00
Chris Lattner
ac76b3c549 Parse inline asm objects 
llvm-svn: 25618
 2006-01-25 22:26:43 +00:00
Chris Lattner
b31becf499 Print InlineAsm objects 
llvm-svn: 25617
 2006-01-25 22:26:05 +00:00
Andrew Lenharth
d932b627f7 make things compile again 
llvm-svn: 25614
 2006-01-25 21:54:38 +00:00
Reid Spencer
f45272f413 Don't break the optimized build (by incorrect placement of #endif) 
llvm-svn: 25613
 2006-01-25 21:49:13 +00:00
Chris Lattner
d36993d81d Change inline asms to be uniqued like constants, not embedded in a Module. 
llvm-svn: 25610
 2006-01-25 18:57:27 +00:00
Chris Lattner
91a347233d initialize an instance var, apparently I forgot to commit this long ago 
llvm-svn: 25609
 2006-01-25 18:57:15 +00:00
Evan Cheng
168b8c5b29 No need to keep track of top and bottom nodes in a group since the vector is 
already in order. Thanks Jim for pointing it out.

llvm-svn: 25608
 2006-01-25 18:54:24 +00:00
Evan Cheng
7da6daadc7 Set SchedulingForLatency to be the default scheduling preference for all. 
llvm-svn: 25607
 2006-01-25 18:52:42 +00:00
Nate Begeman
c29fac7fce First part of bug 680: 
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.

llvm-svn: 25606
 2006-01-25 18:21:52 +00:00
Jeff Cohen
fdbce069c5 Make it even more portable. 
llvm-svn: 25605
 2006-01-25 17:18:50 +00:00
Jeff Cohen
7d0e421a42 Fix VC++ compilation error. 
llvm-svn: 25604
 2006-01-25 17:17:49 +00:00
Evan Cheng
c368fb710f Default scheduling preference is SchedulingForLatency. 
llvm-svn: 25603
 2006-01-25 09:15:54 +00:00
Evan Cheng
46f85ddd84 X86 prefer scheduling for reduced register pressure. 
llvm-svn: 25602
 2006-01-25 09:15:17 +00:00
Evan Cheng
0296933dbe Bottom up register usage reducing list scheduler. 
llvm-svn: 25601
 2006-01-25 09:14:32 +00:00
Evan Cheng
d95c4530e7 Keep track of bottom / top element of a set of flagged nodes. 
llvm-svn: 25600
 2006-01-25 09:13:41 +00:00
Evan Cheng
69d30b1c55 If scheduler choice is the default (-sched=default), use target scheduling 
preference to determine which scheduler to use. SchedulingForLatency ==
Breadth first; SchedulingForRegPressure == bottom up register reduction list
scheduler.

llvm-svn: 25599
 2006-01-25 09:12:57 +00:00
Evan Cheng
b463e81b83 Fix a selectcc lowering bug. Make a copy of X86ISD::CMP when folding it. 
llvm-svn: 25596
 2006-01-25 09:05:09 +00:00
Chris Lattner
8ddb0c3df8 Loosen up these checks to allow direct uses of ESP 
llvm-svn: 25595
 2006-01-25 08:00:36 +00:00
Jeff Cohen
3218a69301 Portably cast a pointer to an integer. 
llvm-svn: 25594
 2006-01-25 02:40:10 +00:00
Duraid Madina
7d51a9b8e3 add bundling! well not really, for now it's just stop-insertion. 
llvm-svn: 25593
 2006-01-25 02:23:38 +00:00
Andrew Lenharth
3b1babbf44 maintaining stackpointer alignment. Perhaps it doesn't matter 
llvm-svn: 25592
 2006-01-25 01:51:08 +00:00
Andrew Lenharth
0940295a7a fix build on 64 bit hosts 
llvm-svn: 25591
 2006-01-24 21:26:43 +00:00
Chris Lattner
84f2acfaa0 Fix Regression/Transforms/ScalarRepl/2006-01-24-IllegalUnionPromoteCrash.ll 
llvm-svn: 25587
 2006-01-24 19:36:27 +00:00
Chris Lattner
f2a2d62f48 use ESP directly, not a copy of ESP into some other register for fastcc calls 
llvm-svn: 25584
 2006-01-24 06:14:44 +00:00
Chris Lattner
cfb7a75ce9 Fix an infinite loop I caused by making sure to legalize the flag operand 
of CALLSEQ_* nodes

llvm-svn: 25582
 2006-01-24 05:48:21 +00:00
Chris Lattner
c078165ea6 Emit the copies out of call return registers *after* the ISD::CALLSEQ_END 
node, fixing fastcc and the case where a function has a frame pointer due
to dynamic allocas.

llvm-svn: 25580
 2006-01-24 05:17:12 +00:00
Chris Lattner
2873307819 Allow jit-beta to work 
llvm-svn: 25578
 2006-01-24 04:50:48 +00:00
Jeff Cohen
ed41a16e5f Fix VC++ compilation error. 
llvm-svn: 25577
 2006-01-24 04:43:17 +00:00
Jeff Cohen
7c5aa59551 Remove unused variables. 
llvm-svn: 25576
 2006-01-24 04:42:53 +00:00
Chris Lattner
d09c95f83c rename method 
llvm-svn: 25572
 2006-01-24 04:16:34 +00:00
Chris Lattner
2cbee3afee Rename method 
llvm-svn: 25571
 2006-01-24 04:14:29 +00:00
Chris Lattner
50ba79e71b Initial checkin of the InlineAsm class 
llvm-svn: 25570
 2006-01-24 04:13:11 +00:00
Jim Laskey
18ba7ce7b3 Crude Dwarf global variable debugging. 
llvm-svn: 25569
 2006-01-24 00:49:18 +00:00
Chris Lattner
c53f8ef744 Pretty print file-scope asm blocks. 
llvm-svn: 25568
 2006-01-24 00:45:30 +00:00
Chris Lattner
239ebe1535 syntax change 
llvm-svn: 25567
 2006-01-24 00:40:17 +00:00
Chris Lattner
ba1b666382 Print file-scope inline asm blocks at the start of the output file. 
llvm-svn: 25565
 2006-01-23 23:47:53 +00:00
Chris Lattner
8f3a1256b7 Add support for reading/writing inline asm 
llvm-svn: 25564
 2006-01-23 23:43:17 +00:00
Chris Lattner
0af0dbcfa5 Add support for linking inline asm 
llvm-svn: 25560
 2006-01-23 23:08:37 +00:00
Chris Lattner
c06c8d8c06 When cloning a module, clone the inline asm. 
llvm-svn: 25559
 2006-01-23 23:06:28 +00:00
Chris Lattner
17eded3dea regenerate 
llvm-svn: 25558
 2006-01-23 23:05:42 +00:00
Chris Lattner
1f9d99295e Add support for parsing global asm blocks 
llvm-svn: 25557
 2006-01-23 23:05:15 +00:00
Chris Lattner
597ab252ea Print out inline asm strings 
llvm-svn: 25556
 2006-01-23 23:03:36 +00:00
Andrew Lenharth
757829acec bye bye Pattern ISEL 
llvm-svn: 25553
 2006-01-23 21:56:07 +00:00
Andrew Lenharth
f7d549848c added stores to lsmark 
llvm-svn: 25552
 2006-01-23 21:51:33 +00:00