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4463 Commits

Author SHA1 Message Date
Bob Wilson
d83b95fd68 Improvements for the Cortex-A9 scheduling itineraries. 
llvm-svn: 129770
 2011-04-19 18:11:36 +00:00
Evan Cheng
e232ee2466 Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That 
is, it assumes addresses are 64-bit aligned (which should be the more common
case). If the alignment is found not to be aligned, then getOperandLatency()
would adjust the operand latency computation by one to compensate for it.
rdar://9294833

llvm-svn: 129742
 2011-04-19 01:21:49 +00:00
Evan Cheng
56c151cba9 Do not lose mem_operands while lowering VLD / VST intrinsics. 
llvm-svn: 129738
 2011-04-19 00:04:03 +00:00
Jim Grosbach
0427f5dec9 Trim a few unneeded includes. 
llvm-svn: 129723
 2011-04-18 21:35:54 +00:00
Sean Callanan
5e7f364b17 Small fix to the ARM AsmParser to ensure that a 
superclass variable is instantiated properly.

llvm-svn: 129713
 2011-04-18 20:20:44 +00:00
Stuart Hastings
4575e2a398 Correct result when a branch condition is live across a block 
boundary.  <rdar://problem/8933028>

llvm-svn: 129634
 2011-04-16 03:31:26 +00:00
Johnny Chen
d7a6b974bc Thumb2 BFC was insufficiently encoded. 
rdar://problem/9292717

llvm-svn: 129619
 2011-04-15 22:52:15 +00:00
Johnny Chen
2a183b813d A8.6.315 VLD3 (single 3-element structure to all lanes) 
The a bit must be encoded as 0.

rdar://problem/9292625

llvm-svn: 129618
 2011-04-15 22:49:08 +00:00
Cameron Zwarich
5e9c2506d8 Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate 
a case involving EOR, so I only added a test for ORR.

llvm-svn: 129610
 2011-04-15 21:24:38 +00:00
Cameron Zwarich
05fb4f0c81 The AND instruction leaves the V flag unmodified, so it falls victim to the same 
problem as all of the other instructions we fold with CMPs.

llvm-svn: 129602
 2011-04-15 20:45:00 +00:00
Cameron Zwarich
ddbf79c32b Add missing register forms of instructions to the ARM CMP-folding code. This 
fixes <rdar://problem/9287901>.

llvm-svn: 129599
 2011-04-15 20:28:28 +00:00
Chris Lattner
0304b82f80 Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Evan Cheng
f33f509d45 Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't 
forget to right shift the source by 32 first. rdar://9287902

llvm-svn: 129556
 2011-04-15 01:31:00 +00:00
Johnny Chen
f268f057f4 For t2BFI, both Inst{26} and Inst{5} "should" be 0. 
Ref: I.1 Instruction encoding diagrams and pseudocode
llvm-svn: 129552
 2011-04-15 00:35:08 +00:00
Johnny Chen
197d67a987 The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions 
(single element or n-element structure to all lanes).

llvm-svn: 129550
 2011-04-15 00:10:45 +00:00
Evan Cheng
d01345fcc4 Follow up on r127913. Fix Thumb revsh isel. rdar://9286766 
llvm-svn: 129548
 2011-04-14 23:27:44 +00:00
Johnny Chen
d58c6d4730 Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. 
llvm-svn: 129531
 2011-04-14 19:13:28 +00:00
Johnny Chen
1362fdf7a6 Thumb disassembler did not handle tBRIND (indirect branch) properly. 
rdar://problem/9280370

llvm-svn: 129480
 2011-04-13 21:59:01 +00:00
Johnny Chen
d4a0b55be5 Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc). 
rdar://problem/9280470

llvm-svn: 129471
 2011-04-13 21:35:49 +00:00
Johnny Chen
dd6fc153b1 The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt. 
rdar://problem/9279440

llvm-svn: 129469
 2011-04-13 21:04:32 +00:00
Cameron Zwarich
6b4e85338c Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>. 
llvm-svn: 129468
 2011-04-13 21:01:19 +00:00
Johnny Chen
b293311a34 Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such. 
rdar://problem/9276651

llvm-svn: 129462
 2011-04-13 19:46:05 +00:00
Johnny Chen
e94b35dc41 Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled. 
rdar://problem/9276427

llvm-svn: 129456
 2011-04-13 17:51:02 +00:00
Johnny Chen
0da4c8bfec Forgot to add this change for http://llvm.org/viewvc/llvm-project?view=rev&revision=129387. 
llvm-svn: 129451
 2011-04-13 16:56:08 +00:00
Cameron Zwarich
86333383eb Fix a typo. 
llvm-svn: 129429
 2011-04-13 06:39:16 +00:00
Johnny Chen
5ae9980472 Add sanity check for Ld/St Dual forms of Thumb2 instructions. 
rdar://problem/9273947

llvm-svn: 129411
 2011-04-12 23:31:00 +00:00
Jakob Stoklund Olesen
b2c47a2087 Add @earlyclobber constraints to the writeback register of all ARM store instructions. 
The ARMARM specifies these instructions as unpredictable when storing the
writeback register. This shouldn't affect code generation much since storing a
pointer to itself is quite rare.

llvm-svn: 129409
 2011-04-12 23:27:48 +00:00
Johnny Chen
e3c070e904 The Thumb2 RFE instructions need to have their second halfword fully specified. 
In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836

llvm-svn: 129391
 2011-04-12 21:41:51 +00:00
Johnny Chen
4450794a69 Add bad register checks for Thumb2 Ld/St instructions. 
rdar://problem/9269047

llvm-svn: 129387
 2011-04-12 21:17:51 +00:00
Johnny Chen
4435fc93c9 The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23} 
be specified as '1' (add = TRUE).

Also add a utility function for Thumb2.

llvm-svn: 129377
 2011-04-12 18:48:00 +00:00
Johnny Chen
aaaa46cee2 Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple. 
llvm-svn: 129365
 2011-04-12 17:09:04 +00:00
Cameron Zwarich
c05412175e Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM 
stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.

llvm-svn: 129345
 2011-04-12 02:24:17 +00:00
Johnny Chen
58713f0ec2 A8.6.16 B 
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;

rdar://problem/9268681

llvm-svn: 129325
 2011-04-12 00:14:49 +00:00
Johnny Chen
443a6902bf Thumb disassembler was erroneously rejecting "blx sp" instruction. 
rdar://problem/9267838

llvm-svn: 129320
 2011-04-11 23:33:30 +00:00
Johnny Chen
77f484c5df Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled. 
rdar://problem/9266265

llvm-svn: 129298
 2011-04-11 21:14:35 +00:00
Owen Anderson
b8c2fc6d09 Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper use of the Commutable bit. 
llvm-svn: 129294
 2011-04-11 20:12:19 +00:00
Johnny Chen
77dc5a7187 Trivial comment fix. 
llvm-svn: 129288
 2011-04-11 18:51:50 +00:00
Johnny Chen
b07cb8fee1 Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as 
invalid instructions.

llvm-svn: 129286
 2011-04-11 18:34:12 +00:00
Kevin Enderby
6e09a5d065 Adding support for printing operands symbolically to llvm's public 'C' 
disassembler API.  Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
  blx _puts
instead of this:
  blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
  movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 129284
 2011-04-11 18:08:50 +00:00
Jay Foad
0d5ca4cf44 Don't include Operator.h from InstrTypes.h. 
llvm-svn: 129271
 2011-04-11 09:35:34 +00:00
Matt Beaumont-Gay
16d2e58f1d Fix an apparent typo that made GCC complain 
llvm-svn: 129160
 2011-04-08 21:59:49 +00:00
Evan Cheng
bc053100af Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time. 
llvm-svn: 129152
 2011-04-08 21:37:21 +00:00
Johnny Chen
18f79bbaca Check opcoe (dmb, dsb) instead of bitfields matching. 
llvm-svn: 129148
 2011-04-08 20:03:46 +00:00
Johnny Chen
e2464aa24a Hanlde the checking of bad regs for SMMLAR properly, instead of asserting. 
PR9650
rdar://problem/9257565

llvm-svn: 129147
 2011-04-08 19:41:22 +00:00
Johnny Chen
5b7854afa5 Sanity check the option operand for DMB/DSB. 
PR9648
rdar://problem/9257634

llvm-svn: 129146
 2011-04-08 19:18:07 +00:00
Jim Grosbach
5e0618da1a Mark hasExtraDefRegAllocReq=1 on LDRD. 
The previous cleanup of LDRD got overzealous and removed it, causing post-RA
scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued.

rdar://9244161

llvm-svn: 129144
 2011-04-08 18:47:05 +00:00
Johnny Chen
16ed2c18a0 Add sanity checking for bad register specifier(s) for the DPFrm instructions. 
Add more test cases to exercise the logical branches related to the above change.

llvm-svn: 129117
 2011-04-08 00:29:09 +00:00
Evan Cheng
9049eb2113 Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183. 
llvm-svn: 129107
 2011-04-07 20:31:12 +00:00
Mon P Wang
9aa67ff50a Fixed encoding for VEXTqf 
llvm-svn: 129101
 2011-04-07 19:56:12 +00:00
Johnny Chen
5d23dd2116 Add sanity checking for invalid register encodings for signed/unsigned extend instructions. 
Add some test cases.

llvm-svn: 129098
 2011-04-07 19:28:58 +00:00