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Commit Graph

147200 Commits

Author SHA1 Message Date
NAKAMURA Takumi
7eceb5c8c8 Reformat.
llvm-svn: 299343
2017-04-02 23:57:10 +00:00
Craig Topper
8fdfc69d58 [APInt] Make use of whichWord and maskBit to simplify some code. NFC
llvm-svn: 299342
2017-04-02 19:35:18 +00:00
Craig Topper
58e7d0ffdd [APInt] Add a public typedef for the internal type of APInt use it instead of integerPart. Make APINT_BITS_PER_WORD and APINT_WORD_SIZE public.
This patch is one step to attempt to unify the main APInt interface and the tc functions used by APFloat.

This patch adds a WordType to APInt and uses that in all the tc functions. I've added temporary typedefs to APFloat to alias it to integerPart to keep the patch size down. I'll work on removing that in a future patch.

In future patches I hope to reuse the tc functions to implement some of the main APInt functionality.

I may remove APINT_ from BITS_PER_WORD and WORD_SIZE constants so that we don't have the repetitive APInt::APINT_ externally.

Differential Revision: https://reviews.llvm.org/D31523

llvm-svn: 299341
2017-04-02 19:17:22 +00:00
Craig Topper
ee73bfe085 [InstCombine] Make InstCombiner::OptAndOp take a BinaryOperator instead of an Instruction.
The callers have already performed the necessary cast before calling. This allows us to remove a comment that says the instruction must be a BinaryOperator and make it explicit in the argument type.

Had to add a default case to the switch because BinaryOperator::getOpcode() returns a BinaryOps enum.

llvm-svn: 299339
2017-04-02 17:57:30 +00:00
Simon Pilgrim
cd51879a46 [X86][MMX] Improve support for folding fptosi from XMM to MMX
llvm-svn: 299338
2017-04-02 17:45:41 +00:00
Craig Topper
0f4f942e8a [InstCombine] Remove redundant combine from visitAnd
As far as I can tell this combine is fully handled by SimplifyDemandedInstructionBits.

I was only looking at this because it is the only user of APIntOps::isShiftedMask which is itself broken. As demonstrated by r299187. I was going to fix isShiftedMask and needed to make sure we had coverage for the new cases it would expose to this combine. But looks like we can nuke it instead.

Differential Revision: https://reviews.llvm.org/D31543

llvm-svn: 299337
2017-04-02 17:34:30 +00:00
Simon Pilgrim
bd73b67ed2 [X86][MMX] Simplify tablegen patterns by always combining MOVDQ2Q from v2i64
llvm-svn: 299336
2017-04-02 16:20:34 +00:00
Simon Pilgrim
8a56903b79 [X86][MMX] Added support for subvector extraction to MMX register
llvm-svn: 299335
2017-04-02 15:52:28 +00:00
NAKAMURA Takumi
4aa469e618 APInt.h: Prune \param(s) in \returns. [-Wdocumentation]
llvm-svn: 299334
2017-04-02 15:05:18 +00:00
Simon Pilgrim
e3f155c3ec Regenerate test with codegen. NFCI.
llvm-svn: 299333
2017-04-02 14:21:14 +00:00
Simon Pilgrim
d54909f415 Regenerate test with codegen. NFCI.
llvm-svn: 299332
2017-04-02 13:59:37 +00:00
Simon Pilgrim
f7f148020e Regenerate test. NFCI.
llvm-svn: 299331
2017-04-02 13:50:44 +00:00
Daniel Berlin
142d8e91ae NewGVN: Handle coercion of constant stores, loads, memory insts.
Summary:
Depends on D30928.

This adds support for coercion of stores and memory instructions that do not require insertion to process.
Another few tests down.
I added the relevant tests from rle.ll

Reviewers: davide

Subscribers: llvm-commits, Prazek

Differential Revision: https://reviews.llvm.org/D30929

llvm-svn: 299330
2017-04-02 13:23:44 +00:00
Nikolai Bozhenov
d971146573 [BypassSlowDivision] Do not bypass division of hash-like values
Disable bypassing if one of the operands looks like a hash value. Slow
division often occurs in hashtable implementations and fast division is
never taken there because a hash value is extremely unlikely to have
enough upper bits set to zero.

A value is considered to be hash-like if it is produced by

1) XOR operation
2) Multiplication by a constant wider than the shorter type
3) PHI node with all incoming values being hash-like

Differential Revision: https://reviews.llvm.org/D28200

llvm-svn: 299329
2017-04-02 13:14:30 +00:00
Simon Pilgrim
e758969660 [X86][MMX] Add generic fptosi 4f32-4i32 test
llvm-svn: 299328
2017-04-02 13:10:20 +00:00
Zvi Rackover
9774a1af3b Add another interesting shufflevector test case for InstSimplify. NFC.
Test case shows opportunity to constant fold a shuffle with one variable
input vector operand.

llvm-svn: 299327
2017-04-02 10:42:21 +00:00
Craig Topper
da5f881e59 [X86] Use tcAdd/tcSubtract to implement the slow case of operator+=/operator-=.
llvm-svn: 299326
2017-04-02 06:59:43 +00:00
Craig Topper
8e1013006a [APInt] Combine declaration and initialization. NFC
llvm-svn: 299325
2017-04-02 06:59:41 +00:00
Craig Topper
65f22f5c12 [APInt] Simplify some code by using operator+=(uint64_t) instead of doing a more complex assignment into a temporary APInt just to use the APInt operator+=.
llvm-svn: 299324
2017-04-02 06:59:38 +00:00
Craig Topper
7ce8f34320 [APInt] Fix typo in comment. NFC
llvm-svn: 299323
2017-04-02 06:59:36 +00:00
Daniel Berlin
3082888e25 MemorySSA: Add support for caching clobbering access in stores
Summary:
This enables us to cache the clobbering access for stores, despite the
fact that we can't rewrite the use-def chains themselves.

Early testing shows that, after this change, for larger testcases, it will be a significant net positive (memory and time) to remove the walker caching.

Reviewers: george.burgess.iv, davide

Subscribers: Prazek, llvm-commits

Differential Revision: https://reviews.llvm.org/D31567

llvm-svn: 299322
2017-04-02 05:09:15 +00:00
Craig Topper
218045c13f [APInt] Use conditional operator to simplify some code. NFC
llvm-svn: 299320
2017-04-01 21:50:10 +00:00
Craig Topper
7700ad04b6 [APInt] Implement flipAllBitsSlowCase with tcComplement. NFCI
llvm-svn: 299319
2017-04-01 21:50:08 +00:00
Craig Topper
0e5c20558b [APInt] Fix indentation. NFC
llvm-svn: 299318
2017-04-01 21:50:06 +00:00
Craig Topper
d23922d24f [APInt] Implement AndAssignSlowCase using tcAnd. Do the same for Or and Xor. NFCI
llvm-svn: 299317
2017-04-01 21:50:03 +00:00
Craig Topper
e205b8c8cd [APInt] Allow GreatestCommonDivisor to take rvalue inputs efficiently. Use moves instead of copies in the loop.
Summary:
GreatestComonDivisor currently makes a copy of both its inputs. Then in the loop we do one move and two copies, plus any allocation the urem call does.

This patch changes it to take its inputs by value so that we can do a move of any rvalue inputs instead of copying. Then in the loop we do 3 move assignments and no copies. This way the only possible allocations we have in the loop is from the urem call.

Reviewers: dblaikie, RKSimon, hans

Reviewed By: dblaikie

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31572

llvm-svn: 299314
2017-04-01 20:30:57 +00:00
Davide Italiano
8876d628b9 [WASM] Remove other comparison of unsigned expression >= 0.
This should finally fix the GCC 7 build with -Werror.

llvm-svn: 299313
2017-04-01 19:47:52 +00:00
Davide Italiano
5012406a6d [WASM] Remove a set but never used variable.
llvm-svn: 299312
2017-04-01 19:40:51 +00:00
Davide Italiano
fe09db437a [WASM] Remove an assertion that can never fire.
uint* is by definition always >=0.

llvm-svn: 299311
2017-04-01 19:37:15 +00:00
Davide Italiano
ccf417eeaa [AMDGPU] Garbage collect now unused dead code. NFCI.
llvm-svn: 299310
2017-04-01 19:30:17 +00:00
Sanjay Patel
69e6407cba [InstSimplify] add constant folding for fdiv/frem
Also, add a helper function so we don't have to repeat this code for each binop.

llvm-svn: 299309
2017-04-01 19:05:11 +00:00
Sanjay Patel
e4f4119624 [InstSimplify] add tests for missed constant folding; NFC
llvm-svn: 299308
2017-04-01 18:44:03 +00:00
Sanjay Patel
8bc0674062 fix formatting; NFC
llvm-svn: 299307
2017-04-01 18:40:30 +00:00
Sanjay Patel
f8e726ee8c fix formatting; NFC
llvm-svn: 299305
2017-04-01 15:53:12 +00:00
Sanjay Patel
4f45c54bbc [DAGCombiner] enable vector transforms for any/all {sign} bits set/clear
The code already allowed vector types in via "isInteger" (which might want
a more specific name), so use splat-friendly constant predicates to match
those types.

llvm-svn: 299304
2017-04-01 15:05:54 +00:00
Sanjay Patel
939ff81f30 [PowerPC, x86] add vector tests for any/all {sign} bits set/clear; NFC
llvm-svn: 299303
2017-04-01 14:32:18 +00:00
Daniel Berlin
d9dab6b15e MemorySSA: Update expensive checking version of def_chain_iterator for templating changes
llvm-svn: 299301
2017-04-01 10:04:28 +00:00
Daniel Berlin
4029b8d144 NewGVN: Don't try to kill off the stored value of stores when
processing the congruence class of the store.
Because we use the stored value of a store as the def, it isn't dead
just because it appears as a def when it comes from a store.

Note: I have not hit any cases with the memory code as it is where
this breaks anything, just because of what memory congruences we
actually allow.  In a followup that improves memory congruence,
this bug actually breaks real stuff (but the verifier catches it).

llvm-svn: 299300
2017-04-01 09:44:33 +00:00
Daniel Berlin
0e411e8719 NewGVN: Clean up GVNExpression memory hierarchy, restructure hash computation a bit so we don't have to redefine it for loads, stores, and calls
llvm-svn: 299299
2017-04-01 09:44:29 +00:00
Daniel Berlin
6c87bef965 NewGVN: Use def_chain iterator in singleReachablePhiPath instead of recursion
llvm-svn: 299298
2017-04-01 09:44:24 +00:00
Daniel Berlin
6ec4612edc Move def_chain iterator to MemorySSA.h so it can be reused
llvm-svn: 299297
2017-04-01 09:44:19 +00:00
Daniel Berlin
2e2452dc6a MemorySSA.h - make clang-format happy
llvm-svn: 299296
2017-04-01 09:44:14 +00:00
Daniel Berlin
d007e8d89f MemorySSA: Push const correctness further.
llvm-svn: 299295
2017-04-01 09:01:12 +00:00
Daniel Berlin
73d62d4a2b MemorySSA: Kill the WalkTargetCache now that we have getBlockDefs.
llvm-svn: 299294
2017-04-01 08:59:45 +00:00
Craig Topper
6b1240150f [APInt] Implement operator! using operator==(uint64_t). NFCI
llvm-svn: 299293
2017-04-01 06:50:00 +00:00
Craig Topper
2e2c462d24 [APInt] Remove the mul/urem/srem/udiv/sdiv functions from the APIntOps namespace. Replace the few usages with calls to the class methods. NFC
llvm-svn: 299292
2017-04-01 05:08:57 +00:00
Craig Topper
aa0b9931a6 [DAGCombiner] Fix fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask) to explicitly ensure that only one of the inputs of each shuffle is a zero vector.
This can only happen when we have a mix of zero and undef elements and the two vectors have a different arrangement of zeros/undefs. The shuffle should eventually be constant folded to all zeros.

Fixes PR32484.

llvm-svn: 299291
2017-04-01 04:26:20 +00:00
Quentin Colombet
a28f69fabd Revert "Feature generic option to setup start/stop-after/before"
This reverts commit r299282.

Didn't intend to commit this :(

llvm-svn: 299288
2017-04-01 01:26:24 +00:00
Quentin Colombet
24093ddd16 Revert "Localizer fun"
This reverts commit r299283.

Didn't intend to commit this :(

llvm-svn: 299287
2017-04-01 01:26:21 +00:00
Quentin Colombet
405ecc5188 Revert "Instrument SDISel C++ patterns"
This reverts commit r299284.

Didn't intend to commit this :(

llvm-svn: 299286
2017-04-01 01:26:17 +00:00