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17236 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
a49a596acf Fixes addc pattern when immediate cannot be represented with 16-bit. Patch by Akira Hatanaka 
llvm-svn: 127005
 2011-03-04 17:59:18 +00:00
Bruno Cardoso Lopes
5400401372 Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira 
llvm-svn: 127003
 2011-03-04 17:51:39 +00:00
Kalle Raiskila
6e33c92ffb Allow vector shifts (shl,lshr,ashr) on SPU. 
There was a previous implementation with patterns that would 
have matched e.g. 
	shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.

llvm-svn: 126998
 2011-03-04 13:19:18 +00:00
Kalle Raiskila
72cfda1a29 Allow load from constant on SPU. 
A 'load <4 x i32>* null' crashes llc before this fix.

llvm-svn: 126995
 2011-03-04 12:00:11 +00:00
Eli Friedman
be07c34368 PR9377: Handle x86 str with register operand in a way consistent with gas. 
llvm-svn: 126970
 2011-03-04 00:10:17 +00:00
Bob Wilson
c48ba54186 PR8053: Fix encoding of S bit in some ARM instructions. 
Patch by Zonr Chang!

llvm-svn: 126967
 2011-03-03 23:07:15 +00:00
Richard Osborne
88d0d840f2 Optimize fprintf -> iprintf if there are no floating point arguments 
and siprintf is available on the target.

llvm-svn: 126940
 2011-03-03 14:20:22 +00:00
Justin Holewinski
396fdaee6d PTX: Fix Emacs renaming a symbol 
llvm-svn: 126938
 2011-03-03 14:09:40 +00:00
Richard Osborne
021b589253 Optimize sprintf -> siprintf if there are no floating point arguments 
and siprintf is available on the target.

llvm-svn: 126937
 2011-03-03 14:09:28 +00:00
Justin Holewinski
86e749c620 PTX: Fix a couple of lint violations 
llvm-svn: 126936
 2011-03-03 13:34:29 +00:00
Richard Osborne
df829ddcb7 Optimize printf -> iprintf if there are no floating point arguments 
and iprintf is available on the target. Currently iprintf is only
marked as being available on the XCore.

llvm-svn: 126935
 2011-03-03 13:17:51 +00:00
Tilmann Scheller
ab6450ec63 Use X86_thiscall calling convention for Win64 as well. 
llvm-svn: 126934
 2011-03-03 07:49:07 +00:00
Bob Wilson
72ccdfe148 Add a readme entry for the redundant movw issue for pr9370. 
llvm-svn: 126930
 2011-03-03 06:39:09 +00:00
Bob Wilson
42f80596ca pr9367: Add missing predicated BLX instructions. 
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

llvm-svn: 126915
 2011-03-03 01:41:01 +00:00
Kevin Enderby
58cc960338 Fixes an assertion failure while disassembling ARM rsbs reg/reg form. 
Patch by Ted Kremenek!

llvm-svn: 126895
 2011-03-02 23:08:33 +00:00
Renato Golin
967b93c6e3 Fixing a bug when printing fpu text to object file. Patch by Mans Rullgard. 
llvm-svn: 126882
 2011-03-02 21:20:09 +00:00
Tilmann Scheller
c557d1eeb4 Add Win64 thiscall calling convention. 
llvm-svn: 126862
 2011-03-02 19:29:22 +00:00
David Greene
2fd6d03bc9 [AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement 
missing patterns for them.

      Add a SIMD test subdirectory to hold tests for SIMD instruction
      selection correctness and quality.
'

llvm-svn: 126845
 2011-03-02 17:23:43 +00:00
Che-Liang Chiou
8ab0f86f1b ptx: fix lint and compiler warnings 
llvm-svn: 126838
 2011-03-02 07:58:46 +00:00
Che-Liang Chiou
3529b49230 Add 64-bit addressing to PTX backend 
- Add '64bit' sub-target option.
- Select 32-bit/64-bit loads/stores based on '64bit' option.
- Fix function parameter order.

Patch by Justin Holewinski

llvm-svn: 126837
 2011-03-02 07:36:48 +00:00
Che-Liang Chiou
2e7bb6da4c Extend initial support for primitive types in PTX backend 
- Allow i16, i32, i64, float, and double types, using the native .u16,
  .u32, .u64, .f32, and .f64 PTX types.
- Allow loading/storing of all primitive types.
- Allow primitive types to be passed as parameters.
- Allow selection of PTX Version and Shader Model as sub-target attributes.
- Merge integer/floating-point test cases for load/store.
- Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler.

Patch by Justin Holewinski

llvm-svn: 126824
 2011-03-02 03:20:28 +00:00
Duncan Sands
859a335e92 Add datalayout information for the IEEE quad precision fp128 type. 
llvm-svn: 126780
 2011-03-01 20:56:50 +00:00
Bill Wendling
304dda7810 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

llvm-svn: 126723
 2011-03-01 01:00:59 +00:00
Chris Lattner
871d62dc5b add a note 
llvm-svn: 126719
 2011-03-01 00:24:51 +00:00
Renato Golin
986151bc09 Fix .fpu printing in ARM assembly, regarding bug http://llvm.org/bugs/show_bug.cgi?id=8931 
llvm-svn: 126689
 2011-02-28 22:04:27 +00:00
Kevin Enderby
da76779962 Add missing whitespace in the formatting. 
llvm-svn: 126687
 2011-02-28 21:45:12 +00:00
Chris Lattner
355d573721 fix a signed comparison warning. 
llvm-svn: 126682
 2011-02-28 20:50:35 +00:00
David Greene
3bc73b0ae9 [AVX] Add decode support for VUNPCKLPS/D instructions, both 128-bit 
and 256-bit forms.  Because the number of elements in a vector
      does not determine the vector type (4 elements could be v4f32 or
      v4f64), pass the full type of the vector to decode routines.

llvm-svn: 126664
 2011-02-28 19:06:56 +00:00
Kevin Enderby
a1c2ea4ba0 Fix the arm's disassembler for blx that was building an MCInst without the 
needed two predicate operands before the imm operand.

llvm-svn: 126662
 2011-02-28 18:46:31 +00:00
Evan Cheng
4e6d375744 Fix a typo which cause dag combine crash. rdar://9059537. 
llvm-svn: 126661
 2011-02-28 18:45:27 +00:00
Stuart Hastings
539d4e1460 Support for byval parameters on ARM. Will be enabled by a forthcoming 
patch to the front-end.  Radar 7662569.

llvm-svn: 126655
 2011-02-28 17:17:53 +00:00
Kalle Raiskila
cc5b703c81 Add branch hinting for SPU. 
The implemented algorithm is overly simplistic (just speculate all branches are
taken)- this is work in progress.

llvm-svn: 126651
 2011-02-28 14:08:24 +00:00
Che-Liang Chiou
4026d01040 Add preliminary support for .f32 in the PTX backend. 
- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
  to accept the float type.
- Add appropriate test cases.

Patch by Justin Holewinski

llvm-svn: 126636
 2011-02-28 06:34:09 +00:00
Benjamin Kramer
0bdf517525 Silence enum conversion warnings. 
llvm-svn: 126578
 2011-02-27 18:13:53 +00:00
NAKAMURA Takumi
b35d45a714 Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit "spill/reload frames" for XMMs. 
It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).

llvm-svn: 126568
 2011-02-27 08:47:19 +00:00
Benjamin Kramer
412ffed4f0 Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic. 
1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible

It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.

llvm-svn: 126557
 2011-02-26 22:48:07 +00:00
Owen Anderson
bd26993873 Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. 
llvm-svn: 126518
 2011-02-25 21:41:48 +00:00
Cameron Zwarich
974208a607 Roll out r126425 and r126450 to see if it fixes the failures on the buildbots. 
llvm-svn: 126488
 2011-02-25 16:30:32 +00:00
Bob Wilson
6bbffe19e9 Add patterns to use post-increment addressing for Neon VST1-lane instructions. 
llvm-svn: 126477
 2011-02-25 06:42:42 +00:00
Evan Cheng
56354c17d9 Fix typo. 
llvm-svn: 126467
 2011-02-25 01:29:29 +00:00
Evan Cheng
fbdcea4b2e Each prologue may have multiple vpush instructions to store callee-saved 
D registers since the vpush list may not have gaps. Make sure the stack
adjustment instruction isn't moved between them. Ditto for vpop in
epilogues.

Sorry, can't reduce a small test case.
rdar://9043312

llvm-svn: 126457
 2011-02-25 00:24:46 +00:00
Chris Lattner
55119c81aa remove command line option debugging hook. 
llvm-svn: 126441
 2011-02-24 21:53:03 +00:00
Devang Patel
f2b2417c2c Enable DebugInfo support for COFF object files. 
Patch by Nathan Jeffords!

llvm-svn: 126425
 2011-02-24 21:04:00 +00:00
Richard Osborne
a8df984a31 Add XCore intrinsic for eeu instruction. 
llvm-svn: 126384
 2011-02-24 13:39:18 +00:00
Evan Cheng
9db7b1367d Fix bug in X86 folding / unfolding table. Int_CMPSDrm and Int_CMPSSrm memory 
operands starts at index 2, not 1.
rdar://9045024
PR9305

llvm-svn: 126359
 2011-02-24 02:36:52 +00:00
Richard Osborne
d9564589f6 Add XCore intrinsic for clre instruction. 
llvm-svn: 126322
 2011-02-23 18:52:05 +00:00
Richard Osborne
4a55817288 Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable 
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.

llvm-svn: 126320
 2011-02-23 18:35:59 +00:00
Richard Osborne
aaac1b01fd Add XCore intrinsic for the setv instruction. 
llvm-svn: 126315
 2011-02-23 16:46:37 +00:00
Richard Osborne
2374e9683e Fix format for setc instruction. 
llvm-svn: 126314
 2011-02-23 15:20:16 +00:00
Richard Osborne
aa39bf94b4 Add XCore intrinsic for settw instruction. 
llvm-svn: 126313
 2011-02-23 14:45:03 +00:00