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dabf739480
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13591 Commits

Author SHA1 Message Date
Johnny Chen
dabf739480 Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm, 
respectively, and add some more comment.

llvm-svn: 99373
 2010-03-24 00:57:50 +00:00
Chris Lattner
36f990dc18 switch SDTBinaryArithWithFlags to be a multiple-result node as well. 
llvm-svn: 99370
 2010-03-24 00:49:29 +00:00
Chris Lattner
0d53d0a634 Switch SDTUnaryArithWithFlags to being modeled as a two-result 
ISD node.  The only change in the generated isel code are comments
like:

<                 // Src: (X86dec_flag:i16 GR16:i16:$src)
---
>                 // Src: (X86dec_flag:i16:i32 GR16:i16:$src)

because now it knows that X86dec_flag returns both an i16 (for the result)
and an i32 (for EFLAGS) in this case.  Wewt.

llvm-svn: 99369
 2010-03-24 00:47:47 +00:00
Chris Lattner
e42b80792e remove 64-bit or_is_add parallels. 
llvm-svn: 99360
 2010-03-24 00:16:52 +00:00
Chris Lattner
6a8da47891 remove useless or_is_add parallel's. 
llvm-svn: 99359
 2010-03-24 00:15:23 +00:00
Chris Lattner
f468453934 reduce nesting. 
llvm-svn: 99358
 2010-03-24 00:12:57 +00:00
Jim Grosbach
b19d22fcae try being more permissive for if-conversion on ARM V7. see what the nightly 
test run permformance numbers say as to whether it helps.

llvm-svn: 99355
 2010-03-24 00:03:13 +00:00
Jakob Stoklund Olesen
1dba4a4389 Revert "Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings." 
This reverts commit 99345. It was breaking buildbots.

llvm-svn: 99352
 2010-03-23 23:48:51 +00:00
Chris Lattner
4eac41e12e [llvm_void_ty] is no longer needed for result types, 
just use an empty result list.

llvm-svn: 99346
 2010-03-23 23:46:07 +00:00
Jakob Stoklund Olesen
9df76f18b4 Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings. 
This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.

llvm-svn: 99345
 2010-03-23 23:14:44 +00:00
Johnny Chen
b7f2a26117 Renamed NVdImmFrm to N1RegModImmFrm. 
llvm-svn: 99344
 2010-03-23 23:09:14 +00:00
Johnny Chen
d97eb200cf Fix typo in the comment for N3VX class. 
llvm-svn: 99328
 2010-03-23 21:35:03 +00:00
Johnny Chen
8249bce25e Add comment. 
llvm-svn: 99327
 2010-03-23 21:30:12 +00:00
Johnny Chen
415ce90919 Add New NEON Format NVdVmVCVTFrm. 
Converted some of the NEON vcvt instructions to this format.

llvm-svn: 99326
 2010-03-23 21:25:38 +00:00
Johnny Chen
81fb570fda Add New NEON Format NVdVmImmFrm. 
llvm-svn: 99322
 2010-03-23 20:40:44 +00:00
Evan Cheng
e6099e3382 Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically? 
llvm-svn: 99320
 2010-03-23 20:35:45 +00:00
Bob Wilson
195c570fd3 Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes. 
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.

llvm-svn: 99309
 2010-03-23 18:54:46 +00:00
Bob Wilson
672147e9a2 Fix bad indentation, 80-column violations, and trailing whitespace. 
llvm-svn: 99295
 2010-03-23 17:23:59 +00:00
Johnny Chen
00ac54b896 Add New NEON Format NVdImmFrm. 
Ref: A7.4.6 One register and a modified immediate value.

llvm-svn: 99288
 2010-03-23 16:43:47 +00:00
Bob Wilson
8ba51dc0bd Rename some instructions to match the corresponding NEON opcode. 
llvm-svn: 99266
 2010-03-23 06:26:18 +00:00
Bob Wilson
58c4740582 Change VST1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.

llvm-svn: 99265
 2010-03-23 06:20:33 +00:00
Bob Wilson
2764399dd8 Change VLD1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

llvm-svn: 99261
 2010-03-23 05:25:43 +00:00
Daniel Dunbar
47743ae59a MC: Add TargetAsmBackend::MayNeedRelaxation, for checking whether a particular instruction + fixups might need relaxation. 
llvm-svn: 99249
 2010-03-23 03:13:05 +00:00
Daniel Dunbar
b33d212057 MC: Add TargetAsmBackend::WriteNopData and use to eliminate some target dependencies in MCMachOStreamer and MCAssembler. 
llvm-svn: 99248
 2010-03-23 02:36:58 +00:00
Daniel Dunbar
1595ebfb4b MC: Add TargetAsmBackend::RelaxInstruction callback, and custom X86 implementation. 
llvm-svn: 99245
 2010-03-23 01:39:09 +00:00
Bob Wilson
0741acde00 Rename one more NEON instruction that I missed earlier. 
llvm-svn: 99201
 2010-03-22 20:31:39 +00:00
Bob Wilson
80b4f21ab7 Regroup some instructions. No functional change. 
llvm-svn: 99192
 2010-03-22 18:22:06 +00:00
Bob Wilson
f23a45e151 Rename some VLD1/VST1 instructions to match the implementation, i.e., the 
corresponding NEON instructions, instead of operation they are currently
used for.

llvm-svn: 99189
 2010-03-22 18:13:18 +00:00
Bob Wilson
8ff1029669 Remove some redundant instruction classes. 
llvm-svn: 99187
 2010-03-22 18:02:38 +00:00
Bob Wilson
0e5d42fb54 Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to 
specify encoding bits in arguments instead of "let" expressions.

llvm-svn: 99185
 2010-03-22 16:43:10 +00:00
Jakob Stoklund Olesen
2b348bdbcd Completely remove Blackfin patterns that thought JustCC was i1. 
Thanks, Chris!

llvm-svn: 99183
 2010-03-22 16:30:04 +00:00
Jeffrey Yasskin
cf13a6f8bb Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters. 
llvm-svn: 99182
 2010-03-22 16:13:21 +00:00
Daniel Dunbar
754ec15462 MC/X86: Fix an MCOperand link, when we parsing shrld $1,%eax and friends; I believe this fixes the last memory leaks under test/MC. 
llvm-svn: 99102
 2010-03-20 22:36:38 +00:00
Daniel Dunbar
2c99d47702 TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects. 
llvm-svn: 99097
 2010-03-20 22:36:22 +00:00
Bob Wilson
e5614d6b2d pr6652: Use LDM to restore PC to the return address on ARMv4. 
Patch by John Tytgat!

llvm-svn: 99096
 2010-03-20 22:20:40 +00:00
Bob Wilson
73d7323c91 Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") 
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.

llvm-svn: 99095
 2010-03-20 22:13:40 +00:00
Bob Wilson
c0f7724ecd Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with 
address register writeback.

llvm-svn: 99094
 2010-03-20 21:57:36 +00:00
Bob Wilson
076aa52a4f Add variants of VST2, VST3 and VST4 with address register writeback, and 
rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.

llvm-svn: 99093
 2010-03-20 21:45:18 +00:00
Bob Wilson
7578eb20da Add instructions for double-spaced VST3 and VST4 without address register 
writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.

llvm-svn: 99090
 2010-03-20 21:15:48 +00:00
Bob Wilson
1106af1257 Add VST1 instructions with address register writeback. 
llvm-svn: 99083
 2010-03-20 20:54:36 +00:00
Bob Wilson
88757e6720 Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with 
address register writeback.

llvm-svn: 99082
 2010-03-20 20:47:18 +00:00
Bob Wilson
e70bdcb2a7 Tidy some more comments and whitespace. 
llvm-svn: 99081
 2010-03-20 20:39:53 +00:00
Bob Wilson
7dacf6bb70 Add variants of VLD2, VLD3 and VLD4 with address register writeback, and 
rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.

llvm-svn: 99080
 2010-03-20 20:10:51 +00:00
Bob Wilson
40ae450fb5 Tidy some comments and whitespace for consistency. 
llvm-svn: 99078
 2010-03-20 19:57:03 +00:00
Bob Wilson
a98f30a3a2 Rename some instructions for consistency and sanity: use "_UPD" suffix for 
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.

llvm-svn: 99066
 2010-03-20 18:35:24 +00:00
Bob Wilson
d275bb2338 Add instructions for double-spaced VLD3 and VLD4 without address register 
writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.

llvm-svn: 99065
 2010-03-20 18:14:26 +00:00
Bob Wilson
045d2c548a Add VLD1 instructions with address register writeback. 
llvm-svn: 99062
 2010-03-20 17:59:03 +00:00
Benjamin Kramer
d621aa79d2 PIC16: Simplify code by using a std::set<std::string> instead of a sorted & uniqued std::list of leaked char*. 
llvm-svn: 99061
 2010-03-20 17:41:18 +00:00
Bob Wilson
3d0c2e0424 Revert the rest of 98679. 
--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U    lib/Target/ARM/ARMInstrVFP.td

llvm-svn: 99049
 2010-03-20 06:34:02 +00:00
Bob Wilson
79c77c16be Fix a very bad typo. Since the register number was off by one, the ARM 
load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.

llvm-svn: 99043
 2010-03-20 06:05:13 +00:00