Elena Demikhovsky
0fec7026d9
Added FMA functionality to X86 target.
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llvm-svn: 161110
2012-08-01 12:06:00 +00:00
Craig Topper
52bf0cfb27
Add intrinsic forms for FMA instructions to opcode folding tables.
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llvm-svn: 157917
2012-06-04 07:46:16 +00:00
Craig Topper
8d3031fa46
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit.
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llvm-svn: 157898
2012-06-03 07:26:46 +00:00
Craig Topper
685b86b007
Use sse_load_f32/64 for scalar FMA3 intrinsic patterns instead of 128-bit loads to match instruction behavior.
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llvm-svn: 157895
2012-06-03 01:40:43 +00:00
Craig Topper
e783584ea7
Add neverHasSideEffects and mayLoad to FMA3 instructions.
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llvm-svn: 157894
2012-06-03 00:30:49 +00:00
Craig Topper
02e5a00a70
Remove fadd(fmul) patterns for FMA3. This needs to be implemented by paying attention to FP_CONTRACT and matching @llvm.fma which is not available yet. This will allow us to enablle intrinsic use at least though.
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llvm-svn: 157804
2012-06-01 06:07:48 +00:00
Craig Topper
6343cc814e
Tidy up. Remove trailing spaces and fix the worst of the 80 column violations.
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llvm-svn: 157799
2012-06-01 05:24:29 +00:00
Elena Demikhovsky
194da7364d
Added FMA3 Intel instructions.
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I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.
llvm-svn: 157737
2012-05-31 09:20:20 +00:00
Jia Liu
6bb2f0f0e4
some comment fix for X86 and ARM
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llvm-svn: 150902
2012-02-19 02:03:36 +00:00
Jia Liu
b077b6085d
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
Craig Topper
4f47613598
Mark scalar FMA4 instructions as ignoring the VEX.L bit.
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llvm-svn: 147602
2012-01-05 08:56:10 +00:00
Craig Topper
089be4fefa
Add FMA4 instructions to disassembler.
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llvm-svn: 147367
2011-12-30 05:20:36 +00:00
Craig Topper
44a5136fac
Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
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llvm-svn: 147366
2011-12-30 04:48:54 +00:00
Craig Topper
97ba7b38eb
Combine FMA4 SS/SD patterns with the instruction definitions.
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llvm-svn: 147365
2011-12-30 03:33:59 +00:00
Craig Topper
bdcc86a43c
Combine FMA4 PS/PD patterns with the instruction definitions.
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llvm-svn: 147364
2011-12-30 03:17:15 +00:00
Craig Topper
33091db89a
Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms.
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llvm-svn: 147361
2011-12-30 02:18:36 +00:00
Craig Topper
e066262284
Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere.
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llvm-svn: 147360
2011-12-30 01:49:53 +00:00
Craig Topper
97e84c23a1
Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions.
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llvm-svn: 147353
2011-12-29 20:43:40 +00:00
Craig Topper
bcfd070378
Expose FMA3 instructions to the disassembler.
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llvm-svn: 147351
2011-12-29 20:03:14 +00:00
Jan Sjödin
fb32802944
Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding.
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llvm-svn: 146151
2011-12-08 14:43:19 +00:00
Jan Sjödin
2dfb343ffa
Support for encoding all FMA4 instructions and tablegen patterns for all
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remaining FMA4 instructions and intrinsics with tests.
llvm-svn: 145525
2011-11-30 22:09:42 +00:00
Bruno Cardoso Lopes
626d04cc6f
This patch contains support for encoding FMA4 instructions and
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tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
llvm-svn: 145133
2011-11-25 19:33:42 +00:00
Bruno Cardoso Lopes
b9182e3051
Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual
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llvm-svn: 109204
2010-07-23 00:54:35 +00:00