Chris Lattner
dc48b6a77c
Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls
...
clobber. This allows LR8 to be save/restored correctly as a 64-bit quantity,
instead of handling it as a 32-bit quantity. This unbreaks ppc64 codegen when
the code is actually located above the 4G boundary.
llvm-svn: 31734
2006-11-14 18:44:47 +00:00
Chris Lattner
10b528d5c3
remove a ton of custom selection logic no longer needed
...
llvm-svn: 31733
2006-11-14 18:43:11 +00:00
Chris Lattner
da103686a6
it would be nice of ctlz were lowered to bsf etc.
...
llvm-svn: 31730
2006-11-14 08:08:46 +00:00
Chris Lattner
e3a81b796c
lower "X = seteq Y, Z" to '(shr (ctlz (xor Y, Z)), 5)' instead of
...
'(shr (ctlz (sub Y, Z)), 5)'.
The use of xor better exposes the operation to bit-twiddling logic in the
dag combiner. For example, this:
typedef struct {
unsigned prefix : 4;
unsigned code : 4;
unsigned unsigned_p : 4;
} tree_common;
int foo(tree_common *a, tree_common *b) {
return a->code == b->code;
}
Now compiles to:
_foo:
lwz r2, 0(r4)
lwz r3, 0(r3)
xor r2, r3, r2
rlwinm r2, r2, 28, 28, 31
cntlzw r2, r2
srwi r3, r2, 5
blr
instead of:
_foo:
lbz r2, 3(r4)
lbz r3, 3(r3)
srwi r2, r2, 4
srwi r3, r3, 4
subf r2, r2, r3
cntlzw r2, r2
srwi r3, r2, 5
blr
saving a cycle.
llvm-svn: 31725
2006-11-14 05:28:08 +00:00
Chris Lattner
8913d79def
add a note
...
llvm-svn: 31719
2006-11-14 01:57:53 +00:00
Chris Lattner
fdffc51d57
minor tweaks, reject vector preinc.
...
llvm-svn: 31717
2006-11-14 01:38:31 +00:00
Evan Cheng
0e82270ff2
Matches MachineInstr changes.
...
llvm-svn: 31712
2006-11-13 23:36:35 +00:00
Chris Lattner
81ea2c7c0a
teach the g5 hazard recognizer about update loads. This fixes
...
Ptrdist/anagram among others.
llvm-svn: 31708
2006-11-13 20:11:06 +00:00
Nick Lewycky
f4f28f415d
Cute example from Chris Lattner.
...
llvm-svn: 31696
2006-11-13 00:23:28 +00:00
Jim Laskey
d692c1a0ab
Make sure stack link is set in 64-bit.
...
llvm-svn: 31690
2006-11-11 22:22:07 +00:00
Chris Lattner
b5aefe29ae
implement proper PPC64 prolog/epilog codegen.
...
llvm-svn: 31684
2006-11-11 19:05:28 +00:00
Jim Laskey
f5bffa5670
Running with frame pointers prevented debugging, external probes and
...
potentially some system calls/exception handling from working. TOS must always
link to previous frame. This is a short term workaround until alloca scheme is
reworked.
llvm-svn: 31677
2006-11-11 10:21:58 +00:00
Evan Cheng
b9e2ae9e37
Add implicit use / def operands to created MI's.
...
llvm-svn: 31676
2006-11-11 10:21:44 +00:00
Evan Cheng
f880ed86ff
Add all implicit defs to FP_REG_KILL mi.
...
llvm-svn: 31674
2006-11-11 07:19:36 +00:00
Chris Lattner
1409347c13
allow the offset of a preinc'd load to be the low-part of a global. This
...
produces this clever code:
_millisecs:
lis r2, ha16(_Time.1182)
lwzu r3, lo16(_Time.1182)(r2)
lwz r2, 4(r2)
addic r4, r2, 1
addze r3, r3
blr
instead of this:
_millisecs:
lis r2, ha16(_Time.1182)
la r3, lo16(_Time.1182)(r2)
lwz r2, lo16(_Time.1182)(r2)
lwz r3, 4(r3)
addic r4, r3, 1
addze r3, r2
blr
for:
long %millisecs() {
%tmp = load long* %Time.1182 ; <long> [#uses=1]
%tmp1 = add long %tmp, 1 ; <long> [#uses=1]
ret long %tmp1
}
llvm-svn: 31673
2006-11-11 04:53:30 +00:00
Chris Lattner
3d48461071
Mark operands as symbol lo instead of imm32 so that they print lo(x) around
...
globals.
llvm-svn: 31672
2006-11-11 04:51:36 +00:00
Chris Lattner
9c5d395b0e
ppc64 doesn't have lwau, don't attempt to form it.
...
llvm-svn: 31656
2006-11-11 00:08:42 +00:00
Chris Lattner
1aaa5f904c
implement preinc support for r+i loads on ppc64
...
llvm-svn: 31654
2006-11-10 23:58:45 +00:00
Evan Cheng
922c8f63b0
Add a note.
...
llvm-svn: 31650
2006-11-10 22:09:17 +00:00
Evan Cheng
8c372dc9b3
These are done.
...
llvm-svn: 31649
2006-11-10 22:03:35 +00:00
Evan Cheng
ae1f3758bd
Don't dag combine floating point select to max and min intrinsics. Those
...
take v4f32 / v2f64 operands and may end up causing larger spills / restores.
Added X86 specific nodes X86ISD::FMAX, X86ISD::FMIN instead.
This fixes PR996.
llvm-svn: 31645
2006-11-10 21:43:37 +00:00
Evan Cheng
3a017e8abd
Fix a bug in SelectScalarSSELoad. Since the load is wrapped in a
...
SCALAR_TO_VECTOR, even if the hasOneUse() check pass we may end up folding
the load into two instructions. Make sure we check the SCALAR_TO_VECTOR
has only one use as well.
llvm-svn: 31641
2006-11-10 21:23:04 +00:00
Chris Lattner
5e975945a5
dform 8/9 are identical to dform 1
...
llvm-svn: 31637
2006-11-10 17:51:02 +00:00
Evan Cheng
de7ff3fa3d
Fix a potential bug.
...
llvm-svn: 31634
2006-11-10 09:13:37 +00:00
Evan Cheng
013597778d
Add implicit def / use operands to MachineInstr.
...
llvm-svn: 31633
2006-11-10 08:43:01 +00:00
Chris Lattner
1604b6a873
add an initial cut at preinc loads for ppc32. This is broken for ppc64
...
(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)
This is disabled unless -enable-ppc-preinc is passed to llc for now.
llvm-svn: 31621
2006-11-10 02:08:47 +00:00
Chris Lattner
15c49af63f
add note about ugly codegen with preinc
...
llvm-svn: 31617
2006-11-10 01:33:53 +00:00
Evan Cheng
6f0095807e
Use TargetInstrInfo::getNumOperands() instead of MachineInstr::getNumOperands(). In preparation for implicit reg def/use changes.
...
llvm-svn: 31616
2006-11-10 01:28:43 +00:00
Anton Korobeynikov
23ffdb1971
Fixing PR990: http://llvm.org/PR990 .
...
This should unbreak csretcc on Linux & mingw targets. Several tests from
llvm-test should be also restored (fftbench, bigfib).
llvm-svn: 31613
2006-11-10 00:48:11 +00:00
Chris Lattner
48d2b0af37
add a note about viterbi
...
llvm-svn: 31612
2006-11-10 00:23:26 +00:00
Evan Cheng
d7df1a37bc
PPC supports i32 / i64 pre-inc load / store.
...
llvm-svn: 31599
2006-11-09 19:11:50 +00:00
Evan Cheng
22bb3ba200
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
...
llvm-svn: 31596
2006-11-09 18:44:21 +00:00
Evan Cheng
89ee587963
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
...
llvm-svn: 31595
2006-11-09 17:55:04 +00:00
Rafael Espindola
5daebfdae0
implement load effective address similar to the alpha backend
...
remove lea_addri and the now unused memri addressing mode
llvm-svn: 31592
2006-11-09 13:58:55 +00:00
Evan Cheng
8743c67826
Remove M_2_ADDR_FLAG.
...
llvm-svn: 31583
2006-11-09 02:22:54 +00:00
Evan Cheng
019b921f3b
Added indexed store node and patfrag's.
...
llvm-svn: 31576
2006-11-08 23:02:11 +00:00
Evan Cheng
2edeb17aed
Use movl+xchgl instead of pushl+popl.
...
llvm-svn: 31572
2006-11-08 20:35:37 +00:00
Evan Cheng
736a8eb3cd
Match tblegen changes.
...
llvm-svn: 31571
2006-11-08 20:34:28 +00:00
Rafael Espindola
f7b898d497
initial implementation of addressing mode 2
...
TODO: fix lea_addri
llvm-svn: 31552
2006-11-08 17:07:32 +00:00
Reid Spencer
da1f5b882a
For PR950:
...
This patch converts the old SHR instruction into two instructions,
AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not
dependent on the sign of their operands.
llvm-svn: 31542
2006-11-08 06:47:33 +00:00
Chris Lattner
bd39c99fd1
Refactor all the addressing mode selection stuff into the isel lowering
...
class, where it can be used for preinc formation.
llvm-svn: 31536
2006-11-08 02:15:41 +00:00
Chris Lattner
35fb10e1a4
correct the (currently unused) pattern for lwzu.
...
llvm-svn: 31535
2006-11-08 02:13:12 +00:00
Evan Cheng
7ca1f47a96
Fixed a bug which causes x86 be to incorrectly match
...
shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.
Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>
llvm-svn: 31519
2006-11-07 22:14:24 +00:00
Chris Lattner
f64e5f5f3e
add a note from viterbi
...
llvm-svn: 31506
2006-11-07 18:30:21 +00:00
Chris Lattner
bed20e1a25
fix encoding of BLR
...
llvm-svn: 31485
2006-11-07 01:51:50 +00:00
Chris Lattner
c3e6822514
add a note
...
llvm-svn: 31477
2006-11-06 21:26:49 +00:00
Jeff Cohen
e1003da1a2
Unbreak VC++ build.
...
llvm-svn: 31464
2006-11-05 19:31:28 +00:00
Reid Spencer
be216ad603
Fix a bug in the last patch and convert to && instead of & for logical expr.
...
llvm-svn: 31463
2006-11-05 19:26:37 +00:00
Reid Spencer
f88c9b1dfc
Implement the -enabled-cbe-printf-a feature.
...
llvm-svn: 31462
2006-11-05 17:09:41 +00:00
Chris Lattner
a193c9c977
encode BLR predicate info for the JIT
...
llvm-svn: 31450
2006-11-04 05:42:48 +00:00