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2560 Commits

Author SHA1 Message Date
Anton Korobeynikov
dca40933ee Honour subreg machine operands during asmprinting 
llvm-svn: 86303
 2009-11-06 23:45:15 +00:00
Bob Wilson
e79354a831 Print VMOV (immediate) operands as hexadecimal values. Apple's assembler 
will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.

llvm-svn: 86301
 2009-11-06 23:33:28 +00:00
Bob Wilson
68772d4db2 Fix a broken test. 
llvm-svn: 86298
 2009-11-06 23:06:42 +00:00
Evan Cheng
aaf30ce699 Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. 
llvm-svn: 86294
 2009-11-06 22:24:13 +00:00
Eric Christopher
593cfc9984 Fix PR5315, original patch by Nicolas Capens! 
llvm-svn: 86203
 2009-11-06 00:11:57 +00:00
Dan Gohman
229f9edf7a Update these tests for the new label names. 
llvm-svn: 86192
 2009-11-05 23:31:40 +00:00
Bob Wilson
641ce17702 Add -mtriple to llc commands, attempting to fix buildbot failures. 
llvm-svn: 86086
 2009-11-05 00:51:31 +00:00
Bob Wilson
d14be3d83c Attempt again to fix buildbot failures: make expected output less specific 
and compile with -mtriple to specify *-apple-darwin targets.

llvm-svn: 86081
 2009-11-05 00:30:35 +00:00
Bob Wilson
25738f9e79 Add PowerPC codegen for indirect branches. 
llvm-svn: 86050
 2009-11-04 21:31:18 +00:00
Bob Wilson
9e30ecad4e Fix broken test. 
llvm-svn: 86045
 2009-11-04 20:04:11 +00:00
Bob Wilson
ca42ca296d Add test for ARM indirectbr codegen. 
llvm-svn: 86042
 2009-11-04 19:25:34 +00:00
Evan Cheng
801415706c RangeIsDefinedByCopyFromReg() should check for subreg_to_reg, insert_subreg, 
and extract_subreg as a "copy" that defines a valno.
Also fixes a typo. These two issues prevent a simple subreg coalescing from
happening before.

llvm-svn: 86022
 2009-11-04 08:33:14 +00:00
Evan Cheng
8b161e8f4f Fix test. 
llvm-svn: 85986
 2009-11-04 00:42:33 +00:00
Evan Cheng
caab17007b fconsts / fconstd immediate should be proceeded with #. 
llvm-svn: 85952
 2009-11-03 21:59:33 +00:00
Evan Cheng
d783406059 Re-apply 85799. It turns out my code isn't buggy. 
llvm-svn: 85947
 2009-11-03 21:40:02 +00:00
Kenneth Uildriks
e711736014 Make opt default to not adding a target data string and update tests that depend on target data to supply it within the test 
llvm-svn: 85900
 2009-11-03 15:29:06 +00:00
Evan Cheng
ed22395c61 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
llvm-svn: 85871
 2009-11-03 05:52:54 +00:00
Nate Begeman
52bcd33312 Declare sin & cos as readonly so they match the code in SelectionDAGBuild 
llvm-svn: 85853
 2009-11-03 02:19:31 +00:00
Anton Korobeynikov
bce2703f18 Temporary xfail until PR5367 will be resolved 
llvm-svn: 85848
 2009-11-03 00:37:36 +00:00
Anton Korobeynikov
48b30c79be Revert r85049, it is causing PR5367 
llvm-svn: 85847
 2009-11-03 00:24:48 +00:00
Evan Cheng
ca5847665b Revert 85799 for now. It might be breaking llvm-gcc driver. 
llvm-svn: 85827
 2009-11-02 21:49:14 +00:00
Evan Cheng
ec5cb0cdbd Initilize the machine LICM CSE map upon the first time an instruction is hoisted to 
the loop preheader. Add instructions which are already in the preheader block that
may be common expressions of those that are hoisted out. These does get a few more
instructions CSE'ed.

llvm-svn: 85799
 2009-11-02 08:09:49 +00:00
Evan Cheng
ce9d8e2737 Remove an irrelevant and poorly reduced test case. 
llvm-svn: 85794
 2009-11-02 07:11:54 +00:00
Evan Cheng
57f7c7c914 Unbreak ARMBaseRegisterInfo::copyRegToReg. 
llvm-svn: 85787
 2009-11-02 04:44:55 +00:00
Anton Korobeynikov
09147da530 Handle splats of undefs properly. This includes the testcase for PR5364 as well. 
llvm-svn: 85767
 2009-11-02 00:12:06 +00:00
Anton Korobeynikov
ed410a8ee3 64-bit FP loads & stores operate on both NEON and VFP pipelines. 
llvm-svn: 85765
 2009-11-02 00:11:06 +00:00
Evan Cheng
4a0d47f209 Make use of imm12 version of Thumb2 ldr / str instructions more aggressively. 
llvm-svn: 85743
 2009-11-01 21:12:51 +00:00
Evan Cheng
0151329ce5 Fix tests. 
llvm-svn: 85723
 2009-11-01 18:13:29 +00:00
Chris Lattner
4cf2980e59 improve x86 codegen support for blockaddress. We now compile 
the testcase into:

_test1:                                                     ## @test1
## BB#0:                                                    ## %entry
	leaq	L_test1_bb6(%rip), %rax
	jmpq	*%rax
L_test1_bb:                                                 ## Address Taken
LBB1_1:                                                     ## %bb
	movb	$1, %al
	ret
L_test1_bb6:                                                ## Address Taken
LBB1_2:                                                     ## %bb6
	movb	$2, %al
	ret

Note, it is very very strange that BlockAddressSDNode doesn't carry 
around TargetFlags.  Dan, please fix this.

llvm-svn: 85703
 2009-11-01 03:25:03 +00:00
Evan Cheng
de16fff3e8 Use cbz and cbnz instructions. 
llvm-svn: 85698
 2009-10-31 23:46:45 +00:00
Jim Grosbach
5b094f3b36 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using 
them for scalar floating point operations for now.

llvm-svn: 85697
 2009-10-31 22:57:36 +00:00
Jim Grosbach
7dfa53d978 Consolidate test files 
llvm-svn: 85696
 2009-10-31 22:20:56 +00:00
Jim Grosbach
acb31ebed1 Change to use FileCheck 
llvm-svn: 85695
 2009-10-31 22:16:14 +00:00
Jim Grosbach
93bcf7b8ce Make tests more explicit about which instructions are expected. 
llvm-svn: 85694
 2009-10-31 22:14:17 +00:00
Jim Grosbach
84e67e8e5c Grammar tweak to comments 
llvm-svn: 85693
 2009-10-31 22:12:44 +00:00
Jim Grosbach
c003ed5615 Update test to be more explicit about what instruction sequences are expected for each operation. 
llvm-svn: 85691
 2009-10-31 22:10:38 +00:00
Jim Grosbach
2a445e5d0a Update test to be more explicit about what instruction sequences are expected for each operation. 
llvm-svn: 85689
 2009-10-31 21:52:58 +00:00
Jim Grosbach
ace75c4288 Expand 64-bit logical shift right inline 
llvm-svn: 85687
 2009-10-31 21:42:19 +00:00
Jim Grosbach
16ae289667 Expand 64-bit arithmetic shift right inline 
llvm-svn: 85685
 2009-10-31 21:00:56 +00:00
Benjamin Kramer
2cc5f86d43 Force triple; darwin's ASM syntax differs from linux's. 
llvm-svn: 85676
 2009-10-31 19:54:06 +00:00
Jim Grosbach
534d2cb249 Expand 64 bit left shift inline rather than using the libcall. For now, this 
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.

llvm-svn: 85675
 2009-10-31 19:38:01 +00:00
Benjamin Kramer
60dac7de40 Add missing colons for FileCheck. 
llvm-svn: 85674
 2009-10-31 19:22:24 +00:00
Jim Grosbach
78a5bcfa02 Convert to FileCheck 
llvm-svn: 85673
 2009-10-31 19:06:53 +00:00
Evan Cheng
9178904e56 It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming. 
llvm-svn: 85643
 2009-10-31 03:39:36 +00:00
Dan Gohman
d5dbd3f588 Add a target triple so that this test behaves consistently across hosts. 
llvm-svn: 85640
 2009-10-31 00:15:28 +00:00
Dan Gohman
14157e31a3 Fix the -mattr line for this test so that it passes on hosts that lack SSSE3. 
llvm-svn: 85637
 2009-10-30 23:18:27 +00:00
Dan Gohman
ad6c6a3d33 Fix MachineLICM to use the correct virtual register class when 
unfolding loads for hoisting.  getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.

llvm-svn: 85622
 2009-10-30 22:18:41 +00:00
Evan Cheng
52d6e56ac9 I forgot to commit this test. 
llvm-svn: 85608
 2009-10-30 20:03:40 +00:00
Rafael Espindola
d4fadd76da This fixes functions like 
void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.

llvm-svn: 85590
 2009-10-30 14:33:14 +00:00
Bob Wilson
f13be9d41e Reimplement BranchFolding change to avoid tail merging for a 1 instruction 
common tail, except when the OptimizeForSize function attribute is present.
Radar 7338114.

llvm-svn: 85441
 2009-10-28 22:10:20 +00:00