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1088 Commits

Author SHA1 Message Date
Chris Lattner
7327c042b4 Add markers in the asm file for tail calls, add a new ADJSTACKPTRri 
sorta-pseudo-instruction

llvm-svn: 22042
 2005-05-15 03:10:37 +00:00
Chris Lattner
64232a8480 Yes, calltarget is the operand of the day. 
llvm-svn: 22040
 2005-05-15 01:10:30 +00:00
Chris Lattner
adb31a99fa When emitting the function epilog, check to see if there already a stack 
adjustment.  If so, we merge the adjustment into the existing one.  This
allows us to generate:

caller2:
        sub %ESP, 12
        mov DWORD PTR [%ESP], 0
        mov %EAX, 1234567890
        mov %EDX, 0
        call func2
        add %ESP, 8
        ret 4

intead of:

caller2:
        sub %ESP, 12
        mov DWORD PTR [%ESP], 0
        mov %EAX, 1234567890
        mov %EDX, 0
        call func2
        sub %ESP, 4
        add %ESP, 12
        ret 4

for X86/fast-cc-merge-stack-adj.ll

llvm-svn: 22038
 2005-05-14 23:53:43 +00:00
Chris Lattner
37e226fa9b Add some new instructions 
llvm-svn: 22036
 2005-05-14 23:35:21 +00:00
Chris Lattner
9d106c705d Pass i64 values correctly split in reg/mem to fastcc calls. 
This fixes fourinarow with -enable-x86-fastcc.

llvm-svn: 22022
 2005-05-14 12:03:10 +00:00
Chris Lattner
adde8b1a71 Use target-specific nodes for calls. This allows the fastcc code to not have 
to do ugly hackery to avoid emitting code like this:

   call foo
   mov vreg, EAX
   adjcallstackup ...

If foo is a fastcc call and if vreg gets spilled, we might end up with this:

   call foo
   mov [ESP+offset], EAX     ;; Offset doesn't consider the 12!
   sub ESP, 12

Which is bad.  The previous hacky code to deal with this was A) gross B) not
good enough.  In particular, it could miss cases and emit the bad code above.
Now we always emit this:

   call foo
   adjcallstackup ...
   mov vreg, EAX

directly.

This makes fastcc with callees poping the stack work much better.  Next
stop (finally!) really is tail calls.

llvm-svn: 22021
 2005-05-14 08:48:15 +00:00
Chris Lattner
c0c6680744 use a target-specific node and custom expander to lower long->FP to FILD64m. 
This should fix some missing symbols problems on BSD and improve performance
of programs that use that operation.

llvm-svn: 22012
 2005-05-14 06:52:07 +00:00
Chris Lattner
2210f7d6e9 Make sure the start of the arg area and the end (after the RA is pushed) 
is always 8-byte aligned for fastcc

llvm-svn: 21995
 2005-05-13 23:49:10 +00:00
Chris Lattner
1634435c77 fix typo 
llvm-svn: 21991
 2005-05-13 22:46:57 +00:00
Chris Lattner
0d4b08e470 Fix the problems with callee popped argument lists 
llvm-svn: 21988
 2005-05-13 22:13:49 +00:00
Chris Lattner
e667c34ef1 Don't emit SAR X, 0 in the case of sdiv Y, 2 
llvm-svn: 21986
 2005-05-13 21:50:27 +00:00
Chris Lattner
fc630bb4f0 Fix UnitTests/2005-05-13-SDivTwo.c 
llvm-svn: 21985
 2005-05-13 21:48:20 +00:00
Chris Lattner
62593e4e66 switch to having the callee pop stack operands for fastcc. This is currently buggy 
do not use

llvm-svn: 21984
 2005-05-13 21:44:04 +00:00
Chris Lattner
e9944b033d allow RETI 
llvm-svn: 21980
 2005-05-13 20:46:35 +00:00
Chris Lattner
2c9d871f9b Build TAILCALL nodes in LowerCallTo, treat them like normal calls everywhere. 
llvm-svn: 21976
 2005-05-13 20:29:13 +00:00
Chris Lattner
9d788e93a6 Add an isTailCall flag to LowerCallTo 
llvm-svn: 21958
 2005-05-13 18:50:42 +00:00
Chris Lattner
83d7e55471 add 'ret imm' instruction 
llvm-svn: 21945
 2005-05-13 17:56:48 +00:00
Chris Lattner
7c3b219c28 Do not CopyFromReg physregs for live-in values. Instead, create a vreg for 
each live in, and copy the regs from the vregs.  As the very first thing we
do in the function, insert copies from the pregs to the vregs.  This fixes
problems where the token chain of CopyFromReg was not enough to allow reordering
of the copyfromreg nodes and other unchained nodes (e.g. div, which clobbers
eax on intel).

llvm-svn: 21932
 2005-05-13 07:38:09 +00:00
Chris Lattner
094bbfcebb rename the ADJCALLSTACKDOWN/ADJCALLSTACKUP nodes to be CALLSEQ_START/BEGIN. 
llvm-svn: 21915
 2005-05-12 23:24:06 +00:00
Chris Lattner
3106dfa185 Add a new -enable-x86-fastcc option that enables passing the first 
two integer values in registers for the fastcc calling conv.

llvm-svn: 21912
 2005-05-12 23:06:28 +00:00
Chris Lattner
7e08dd591c Pass in Calling Convention to use into LowerCallTo 
llvm-svn: 21899
 2005-05-12 19:56:45 +00:00
Chris Lattner
d8766cdae2 Enable pattern isel by default 
llvm-svn: 21898
 2005-05-12 19:56:09 +00:00
Chris Lattner
e358ac532b X86 has more than just 32-bit registers 
llvm-svn: 21857
 2005-05-11 05:00:34 +00:00
Chris Lattner
8230bddde2 Convert feature of the simple isel over for the pattern isel to use. 
llvm-svn: 21840
 2005-05-10 03:53:18 +00:00
Jeff Cohen
afc58006b7 Silence some VC++ warnings 
llvm-svn: 21838
 2005-05-10 02:22:38 +00:00
Chris Lattner
d96aea21d7 Implement READPORT/WRITEPORT, implementing the last X86 regression tests 
that were failing with the pattern selector.  Note that the support that
existed in the simple selector was clearly broken in several ways though
(which has also been fixed).

llvm-svn: 21831
 2005-05-09 21:17:38 +00:00
Chris Lattner
6a55b1d4dd do not emit illegal instructions 
llvm-svn: 21830
 2005-05-09 21:06:04 +00:00
Chris Lattner
7ba0699b05 Fix the syntax of the i/o instructions, these are obviously unused. 
llvm-svn: 21829
 2005-05-09 20:49:20 +00:00
Chris Lattner
46b51ab388 legalize readio/writeio into load/stores, fixing CodeGen/X86/io.llx with 
the pattern isel.

llvm-svn: 21828
 2005-05-09 20:37:29 +00:00
Chris Lattner
b28f865865 restore some non-dead code I removed last night breaking double casts to 
uint

llvm-svn: 21821
 2005-05-09 18:37:02 +00:00
Chris Lattner
3094cec3c9 Wrap long lines, remove dead code that is now handled by legalize 
llvm-svn: 21811
 2005-05-09 05:40:26 +00:00
Chris Lattner
5d291fa443 Fix FP -> bool casts 
llvm-svn: 21810
 2005-05-09 05:33:18 +00:00
Chris Lattner
65d61d9d44 Fix X86/2005-05-08-FPStackifierPHI.ll: ugly gross hack. 
llvm-svn: 21801
 2005-05-09 03:36:39 +00:00
Andrew Lenharth
8e2beec4d1 fix typo 
llvm-svn: 21693
 2005-05-04 19:25:37 +00:00
Andrew Lenharth
8b64bd0fd5 Implement count leading zeros (ctlz), count trailing zeros (cttz), and count 
population (ctpop).  Generic lowering is implemented, however only promotion
is implemented for SelectionDAG at the moment.

More coming soon.

llvm-svn: 21676
 2005-05-03 17:19:30 +00:00
Chris Lattner
15d29b0220 Add support for FSIN/FCOS when unsafe math ops are enabled. Patch contributed by 
Morten Ofstad!

llvm-svn: 21632
 2005-04-30 04:25:35 +00:00
Chris Lattner
663664d10c Add support for llvm.sqrt and sin/cos if unsafe math optimizations are enabled. 
llvm-svn: 21631
 2005-04-30 04:12:40 +00:00
Chris Lattner
27a534f181 Add support for FSQRT node, patch contributed by Morten Ofstad 
llvm-svn: 21610
 2005-04-28 22:07:18 +00:00
Chris Lattner
236cef3563 Add some new X86 instrs, patch contributed by Morten Ofstad 
llvm-svn: 21608
 2005-04-28 21:50:05 +00:00
Chris Lattner
2f7a83ffbf Codegen fabs/fabsf as FABS. Patch contributed by Morten Ofstad 
llvm-svn: 21607
 2005-04-28 21:48:42 +00:00
Andrew Lenharth
2a00530fa7 Implement Value* tracking for loads and stores in the selection DAG. This enables one to use alias analysis in the backends. 
(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*.  Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.

llvm-svn: 21599
 2005-04-27 20:10:01 +00:00
Misha Brukman
bf3f6181fd * Remove trailing whitespace 
* Convert tabs to spaces

llvm-svn: 21426
 2005-04-21 23:38:14 +00:00
Chris Lattner
8d813a7d51 Handle stores of global address as stores of immediates. Instead of: 
test1:
        movl $N, %eax
        movl %eax, G
        ret

emit:

test1:
        movl $N, G
        ret

llvm-svn: 21407
 2005-04-21 19:11:03 +00:00
Chris Lattner
706775467b Handle (store &GV -> mem) as a store immediate. This often occurs for 
printf format strings and other stuff.  Instead of generating this:

        movl $l1__2E_str_1, %eax
        movl %eax, (%esp)

we now emit:

        movl $l1__2E_str_1, (%esp)

llvm-svn: 21406
 2005-04-21 19:03:24 +00:00
Nate Begeman
ecb5b5c028 Make pattern isel default for ppc 
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
  0 == off
  1 == on
  2 == target default

llvm-svn: 21309
 2005-04-15 22:12:16 +00:00
Chris Lattner
85c6a7bed0 Fix some mysteriously missing {}'s which cause the miscompilation of 
Olden/mst, Ptrdist/bc, Obsequi, etc.

llvm-svn: 21274
 2005-04-13 03:29:53 +00:00
Chris Lattner
f25fefd9cf Z_E_I is gone 
llvm-svn: 21267
 2005-04-13 02:39:05 +00:00
Chris Lattner
fd4d6e0847 Use live out sets for return values instead of imp_defs, which is cleaner and faster. 
llvm-svn: 21181
 2005-04-09 15:23:56 +00:00
Chris Lattner
39f963f968 This target does not support/want ISD::BRCONDTWOWAY 
llvm-svn: 21164
 2005-04-09 03:22:37 +00:00
Chris Lattner
583dcc66f2 X86 zero extends setcc results 
llvm-svn: 21146
 2005-04-07 19:41:46 +00:00
Chris Lattner
40ee8a062b Fix SingleSource/Regression/C/2005-05-06-LongLongSignedShift.c, we were not 
properly sign extending the top of the result of a 64-bit shift right by
a constant > 32.

llvm-svn: 21120
 2005-04-06 20:59:35 +00:00
Chris Lattner
c87ff88efb Add (untested) support for MULHS and MULHU. 
llvm-svn: 21107
 2005-04-06 04:21:07 +00:00
Chris Lattner
ba7cdbebb1 add signed versions of the extra precision multiplies 
llvm-svn: 21106
 2005-04-06 04:19:22 +00:00
Chris Lattner
8f30d63c1a add support for FABS and FNEG 
llvm-svn: 21015
 2005-04-02 05:30:17 +00:00
Chris Lattner
a5d4718875 This target doesn't support fabs/fneg yet. 
llvm-svn: 21010
 2005-04-02 05:03:24 +00:00
Chris Lattner
71434aa2dd add an fabs instr 
llvm-svn: 21006
 2005-04-02 04:31:56 +00:00
Chris Lattner
8ee783d9f0 Add support for 64-bit shifts. 
llvm-svn: 21005
 2005-04-02 04:01:14 +00:00
Chris Lattner
67da3fdb70 Add support for ISD::UNDEF to the X86 be 
llvm-svn: 20990
 2005-04-01 22:46:45 +00:00
Chris Lattner
46c4246df1 don't depend on the cfg being set up yet 
llvm-svn: 20936
 2005-03-30 01:10:00 +00:00
Nate Begeman
f821401825 Change interface to LowerCallTo to take a boolean isVarArg argument. 
llvm-svn: 20842
 2005-03-26 01:29:23 +00:00
Chris Lattner
ad07b1bc54 eliminate dead variables, patch contributed by Gabor Greif! 
llvm-svn: 20812
 2005-03-24 17:32:20 +00:00
Nate Begeman
175a9f1cc6 Remove comments that are now meaningless from the pattern ISels, at Chris's 
request.

llvm-svn: 20804
 2005-03-24 04:39:54 +00:00
Chris Lattner
79ba9d58fd Don't emit two comparisons when comparing a FP value against zero! 
llvm-svn: 20651
 2005-03-17 16:29:26 +00:00
Chris Lattner
c9a3ea81bf Fix the missing symbols problem Bill was hitting. Patch contributed by 
Bill Wendling!!

llvm-svn: 20649
 2005-03-17 15:38:16 +00:00
Chris Lattner
4b688a1c70 This mega patch converts us from using Function::a{iterator|begin|end} to 
using Function::arg_{iterator|begin|end}.  Likewise Module::g* -> Module::global_*.

This patch is contributed by Gabor Greif, thanks!

llvm-svn: 20597
 2005-03-15 04:54:21 +00:00
Reid Spencer
b0ca4aa8cd Patch to make assembly output compatible with mingw compilation (identical 
to cygwin)

llvm-svn: 20520
 2005-03-08 17:02:05 +00:00
Chris Lattner
a024984017 Fix spelling, patch contributed by Gabor Greif! 
llvm-svn: 20343
 2005-02-27 06:18:25 +00:00
Chris Lattner
9838ab1271 Silence some uninit variable warnings. 
llvm-svn: 20284
 2005-02-23 05:57:21 +00:00
Chris Lattner
ab92b92bc5 We can fold promoted and non-promoted loads into divs also! 
llvm-svn: 19835
 2005-01-25 20:35:10 +00:00
Chris Lattner
a9a0369879 Fold promoted loads into binary ops for FP, allowing us to generate m32 forms 
of FP ops.

llvm-svn: 19834
 2005-01-25 20:03:11 +00:00
Chris Lattner
6ff85c3152 Silence a warning. 
llvm-svn: 19798
 2005-01-23 23:20:06 +00:00
Chris Lattner
94952e0947 Allow the FP stackifier to completely ignore functions that do not use FP at 
all.  This should speed up the X86 backend fairly significantly on integer
codes.  Now if only we didn't have to compute livevar still... ;-)

llvm-svn: 19796
 2005-01-23 23:13:59 +00:00
Reid Spencer
5c7b6e83f0 Support Cygwin assembly generation. The cygwin version of Gnu ASsembler 
doesn't support certain directives and symbols on cygwin are prefixed with
an underscore. This patch makes the necessary adjustments to the output.

llvm-svn: 19775
 2005-01-23 03:52:14 +00:00
Chris Lattner
b4cf4ffb04 Speed up folding operations into loads. 
llvm-svn: 19733
 2005-01-21 21:43:02 +00:00
Chris Lattner
fd4d7f71ae The ever-important vanity pass name :) 
llvm-svn: 19731
 2005-01-21 21:35:14 +00:00
Chris Lattner
5f2fbeaa69 Fix a FIXME: realize that argument stores are all independent (don't alias) 
llvm-svn: 19728
 2005-01-21 19:46:38 +00:00
Chris Lattner
febeb380ae Implement ADD_PARTS/SUB_PARTS so that 64-bit integer add/sub work. This 
fixes most of the remaining llc-beta failures.

llvm-svn: 19716
 2005-01-20 18:53:00 +00:00
Chris Lattner
8b0a2a3251 Fix a crash compiling 134.perl. 
llvm-svn: 19711
 2005-01-20 16:50:16 +00:00
Chris Lattner
6534e1ede3 Fix a problem where were were literally selecting for INCREASED register 
pressure, not decreases register pressure.  Fix problem where we accidentally
swapped the operands of SHLD, which caused fourinarow to fail.  This fixes
fourinarow.

llvm-svn: 19697
 2005-01-19 17:24:34 +00:00
Chris Lattner
b75589131d When commuting these instructions, make sure to actually swap the operands too. 
llvm-svn: 19694
 2005-01-19 16:55:52 +00:00
Chris Lattner
fde1a5688b Implement Regression/CodeGen/X86/rotate.ll: emit rotate instructions (which 
typically cost 1 cycle) instead of shld/shrd instruction (which are typically
6 or more cycles).  This also saves code space.

For example, instead of emitting:

rotr:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %CL, BYTE PTR [%ESP + 8]
        shrd %EAX, %EAX, %CL
        ret
rotli:
        mov %EAX, DWORD PTR [%ESP + 4]
        shrd %EAX, %EAX, 27
        ret

Emit:

rotr32:
        mov %CL, BYTE PTR [%ESP + 8]
        mov %EAX, DWORD PTR [%ESP + 4]
        ror %EAX, %CL
        ret
rotli32:
        mov %EAX, DWORD PTR [%ESP + 4]
        ror %EAX, 27
        ret

We also emit byte rotate instructions which do not have a sh[lr]d counterpart
at all.

llvm-svn: 19692
 2005-01-19 08:07:05 +00:00
Chris Lattner
34757ff939 Add rotate instructions. 
llvm-svn: 19690
 2005-01-19 07:50:03 +00:00
Chris Lattner
e539ce8223 Match 16-bit shld/shrd instructions as well, implementing shift-double.llx:test5 
llvm-svn: 19689
 2005-01-19 07:37:26 +00:00
Chris Lattner
9d5ee289d7 Improve coverage of the X86 instruction set by adding 16-bit shift doubles. 
llvm-svn: 19687
 2005-01-19 07:31:24 +00:00
Chris Lattner
c03f360215 Teach the code generator that shrd/shld is commutable if it has an immediate. 
This allows us to generate this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        shld %EDX, %EDX, 2
        shl %EAX, 2
        ret

instead of this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EDX, %EAX
        shrd %EDX, %ECX, 30
        shl %EAX, 2
        ret

Note the magically transmogrifying immediate.

llvm-svn: 19686
 2005-01-19 07:11:01 +00:00
Chris Lattner
575e912fcf Codegen long >> 2 to this: 
foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        shrd %EAX, %EDX, 2
        sar %EDX, 2
        ret

instead of this:

test1:
        mov %ECX, DWORD PTR [%ESP + 4]
        shr %ECX, 2
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %EAX, %EDX
        shl %EAX, 30
        or %EAX, %ECX
        sar %EDX, 2
        ret

and long << 2 to this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
***     mov %EDX, %EAX
        shrd %EDX, %ECX, 30
        shl %EAX, 2
        ret

instead of this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, %EAX
        shr %ECX, 30
        mov %EDX, DWORD PTR [%ESP + 8]
        shl %EDX, 2
        or %EDX, %ECX
        shl %EAX, 2
        ret

The extra copy (marked ***) can be eliminated when I teach the code generator
that shrd32rri8 is really commutative.

llvm-svn: 19681
 2005-01-19 06:18:43 +00:00
Chris Lattner
419a5d213b X86 shifts mask the amount. 
llvm-svn: 19678
 2005-01-19 03:36:30 +00:00
Chris Lattner
6dec8cb829 Code to handle FP_EXTEND is dead now. X86 doesn't support any data types to 
FP_EXTEND from!

llvm-svn: 19674
 2005-01-18 20:05:56 +00:00
Chris Lattner
798e9c85d6 Remove more dead code. 
llvm-svn: 19673
 2005-01-18 19:50:08 +00:00
Chris Lattner
401814508f The selection dag code handles the promotions from F32 to F64 for us, so we 
don't need to even think about F32 in the X86 code anymore.

llvm-svn: 19672
 2005-01-18 19:46:54 +00:00
Chris Lattner
dc09e52b3e Fix 124.m88ksim. 
llvm-svn: 19667
 2005-01-18 17:35:28 +00:00
Chris Lattner
a04b1ee7a8 Do not emit loads multiple times, potentially in the wrong places. 
llvm-svn: 19661
 2005-01-18 04:18:32 +00:00
Chris Lattner
722ddeb86e Eliminate bad assertions. 
llvm-svn: 19659
 2005-01-18 04:00:54 +00:00
Chris Lattner
8f3a8d96e2 * Eliminate the TokenSet and just use the ExprMap for both tokens and values. 
* Insert some really pedantic assertions that will notice when we emit the
  same loads more than one time, exposing bugs.  This turns a miscompilation in
  bzip2 into a compile-fail.  yaay.

llvm-svn: 19658
 2005-01-18 03:51:59 +00:00
Chris Lattner
b3edb09ede Rely on the code in MatchAddress to do this work. Otherwise we fail to 
match (X+Y)+(Z << 1), because we match the X+Y first, consuming the index
register, then there is no place to put the Z.

llvm-svn: 19652
 2005-01-18 02:25:52 +00:00
Chris Lattner
ce2e0125dc Fix a problem where probing for addressing modes caused expressions to be 
emitted too early.  In particular, this fixes
Regression/CodeGen/X86/regpressure.ll:regpressure3.

This also improves the 2nd basic block in 164.gzip:flush_block, which went from

.LBBflush_block_1:      # loopentry.1.i
        movzx %EAX, WORD PTR [dyn_ltree + 20]
        movzx %ECX, WORD PTR [dyn_ltree + 16]
        mov DWORD PTR [%ESP + 32], %ECX
        movzx %ECX, WORD PTR [dyn_ltree + 12]
        movzx %EDX, WORD PTR [dyn_ltree + 8]
        movzx %EBX, WORD PTR [dyn_ltree + 4]
        mov DWORD PTR [%ESP + 36], %EBX
        movzx %EBX, WORD PTR [dyn_ltree]
        add DWORD PTR [%ESP + 36], %EBX
        add %EDX, DWORD PTR [%ESP + 36]
        add %ECX, %EDX
        add DWORD PTR [%ESP + 32], %ECX
        add %EAX, DWORD PTR [%ESP + 32]
        movzx %ECX, WORD PTR [dyn_ltree + 24]
        add %EAX, %ECX
        mov %ECX, 0
        mov %EDX, %ECX

to

.LBBflush_block_1:      # loopentry.1.i
        movzx %EAX, WORD PTR [dyn_ltree]
        movzx %ECX, WORD PTR [dyn_ltree + 4]
        add %ECX, %EAX
        movzx %EAX, WORD PTR [dyn_ltree + 8]
        add %EAX, %ECX
        movzx %ECX, WORD PTR [dyn_ltree + 12]
        add %ECX, %EAX
        movzx %EAX, WORD PTR [dyn_ltree + 16]
        add %EAX, %ECX
        movzx %ECX, WORD PTR [dyn_ltree + 20]
        add %ECX, %EAX
        movzx %EAX, WORD PTR [dyn_ltree + 24]
        add %ECX, %EAX
        mov %EAX, 0
        mov %EDX, %EAX

... which results in less spilling in the function.

This change alone speeds up 164.gzip from 37.23s to 36.24s on apoc.  The
default isel takes 37.31s.

llvm-svn: 19650
 2005-01-18 01:06:26 +00:00
Chris Lattner
a78f9ced61 Fix indentation. 
llvm-svn: 19649
 2005-01-17 23:25:45 +00:00
Chris Lattner
dff1e3e86f Don't bother using max here. 
llvm-svn: 19647
 2005-01-17 23:02:13 +00:00
Chris Lattner
2d86b43318 Do not give token factor nodes outrageous weights 
llvm-svn: 19645
 2005-01-17 22:56:09 +00:00
Chris Lattner
f2878ce8ba Two changes: 
1. Fold  [mem] += (1|-1) into inc [mem]/dec [mem] to save some icache space.
 2. Do not let token factor nodes prevent forming '[mem] op= val' folds.

llvm-svn: 19643
 2005-01-17 22:10:42 +00:00