Jim Grosbach
dd667a11d3
NEON VLD3 lane-indexed assembly parsing and encoding.
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llvm-svn: 148734
2012-01-23 21:53:26 +00:00
Jim Grosbach
0eeacbfe2e
Simplify some NEON assembly pseudo definitions.
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Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
llvm-svn: 148718
2012-01-23 19:39:08 +00:00
Jim Grosbach
4579f05f36
NEON use vmov.i32 to splat some f32 values into vectors.
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For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.
rdar://10616677
llvm-svn: 148556
2012-01-20 18:09:51 +00:00
Jim Grosbach
b7ab9edb4e
Thumb2 alternate syntax for LDR(literal) and friends.
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Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
llvm-svn: 148432
2012-01-18 22:46:46 +00:00
Jim Grosbach
a678ad9ecc
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
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rdar://10558523
llvm-svn: 147189
2011-12-22 22:19:05 +00:00
Rafael Espindola
eba1c0eb00
Fix incorrect relocation generation. Patch by Kristof Beyls.
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Fixes PR11214.
llvm-svn: 147180
2011-12-22 21:36:43 +00:00
Jim Grosbach
100e3aaffa
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
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Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
llvm-svn: 147153
2011-12-22 18:04:04 +00:00
Jim Grosbach
7d31680e2d
ARM VFP optional data type on VMOV GPR<-->SPR.
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llvm-svn: 147104
2011-12-21 23:24:15 +00:00
Jim Grosbach
2bbc41fa26
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
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Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
llvm-svn: 147096
2011-12-21 21:04:19 +00:00
Jim Grosbach
91faf5d15f
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
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These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
llvm-svn: 147094
2011-12-21 20:54:00 +00:00
Jim Grosbach
f7236d1084
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
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llvm-svn: 147069
2011-12-21 19:40:55 +00:00
Jim Grosbach
6bd1044b03
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
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llvm-svn: 147025
2011-12-21 00:38:54 +00:00
Jim Grosbach
0768f2c420
Enable and fix a test.
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llvm-svn: 147011
2011-12-20 23:20:00 +00:00
Jim Grosbach
8978194025
ARM assembly parsing and encoding for VST2 single-element, double spaced.
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llvm-svn: 146990
2011-12-20 20:46:29 +00:00
Jim Grosbach
3f48367a1b
ARM enable a few more tests.
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llvm-svn: 146985
2011-12-20 20:03:00 +00:00
Jim Grosbach
8156a5dcee
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
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llvm-svn: 146983
2011-12-20 19:21:26 +00:00
Jim Grosbach
3f5493c136
ARM assembly shifts by zero should be plain 'mov' instructions.
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"mov r1, r2, lsl #0 " should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
Jim Grosbach
343f270350
ARM assembly parsing and encoding support for LDRD(label).
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rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
Jim Grosbach
797a88284c
ARM NEON two-operand aliases for VPADD.
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rdar://10602276
llvm-svn: 146895
2011-12-19 19:51:03 +00:00
Jim Grosbach
520db82971
ARM NEON implied destination aliases for VMAX/VMIN.
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llvm-svn: 146885
2011-12-19 18:57:38 +00:00
Jim Grosbach
f4ca84a7ab
ARM NEON relax parse time diagnostics for alignment specifiers.
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There's more variation that we need to handle. Error checking will need
to be on operand predicates.
llvm-svn: 146884
2011-12-19 18:31:43 +00:00
Jim Grosbach
30f4b285a6
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
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llvm-svn: 146699
2011-12-15 22:56:33 +00:00
Jim Grosbach
b79d2a8f50
ARM NEON VTBL/VTBX assembly parsing and encoding.
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llvm-svn: 146691
2011-12-15 22:27:11 +00:00
Jim Grosbach
75db252aee
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
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llvm-svn: 146605
2011-12-14 23:25:46 +00:00
Jim Grosbach
83520a5b70
ARM NEON fix alignment encoding for VST2 w/ writeback.
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Add tests for w/ writeback instruction parsing and encoding.
llvm-svn: 146594
2011-12-14 21:49:24 +00:00
Jim Grosbach
44829ab9d2
ARM NEON VST2 assembly parsing and encoding.
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Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
Jim Grosbach
54372eef76
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
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When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
llvm-svn: 146567
2011-12-14 17:30:24 +00:00
Jim Grosbach
628ae663ef
ARM assembler support for the target-specific .req directive.
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rdar://10549683
llvm-svn: 146543
2011-12-14 02:16:11 +00:00
Jim Grosbach
089ad574d8
Thumb2 assembler aliases for "mov(shifted register)"
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rdar://10549767
llvm-svn: 146520
2011-12-13 22:45:11 +00:00
Jim Grosbach
bd33fc6efd
ARM LDM/STM system instruction variants.
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rdar://10550269
llvm-svn: 146519
2011-12-13 21:48:29 +00:00
Jim Grosbach
7db50010cc
Test for 146516
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llvm-svn: 146517
2011-12-13 21:06:59 +00:00
Jim Grosbach
13d3509445
ARM thumb2 parsing of "rsb rd, rn, #0 ".
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rdar://10549741
llvm-svn: 146515
2011-12-13 20:50:38 +00:00
Jim Grosbach
dfec87fe2f
ARM NEON two-operand aliases for VQDMULH.
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llvm-svn: 146514
2011-12-13 20:40:37 +00:00
Jim Grosbach
0ba5ba4535
ARM pre-UAL NEG mnemonic for convenience when porting old code.
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llvm-svn: 146511
2011-12-13 20:23:22 +00:00
Jim Grosbach
356ad6d232
ARM assembly aliases for BIC<-->AND (immediate).
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When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
llvm-svn: 146283
2011-12-09 22:02:17 +00:00
Jim Grosbach
489e81da30
ARM assembly parsing and encoding for VLD2 with writeback.
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Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
2011-12-09 21:28:25 +00:00
Jim Grosbach
62873cae5f
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
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llvm-svn: 146194
2011-12-08 22:19:04 +00:00
Jim Grosbach
a33fa8aa88
ARM VSHR implied destination operand form aliases.
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llvm-svn: 146192
2011-12-08 22:06:06 +00:00
Jim Grosbach
af9cc198cf
Tidy up a bit.
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llvm-svn: 146190
2011-12-08 22:04:40 +00:00
Jim Grosbach
78020c4642
ARM VSUB implied destination operand form aliases.
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llvm-svn: 146182
2011-12-08 20:56:26 +00:00
Jim Grosbach
957be45ccf
Tidy up a bit.
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llvm-svn: 146181
2011-12-08 20:53:19 +00:00
Jim Grosbach
a33af36947
ARM VQADD implied destination operand form aliases.
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llvm-svn: 146179
2011-12-08 20:49:43 +00:00
Jim Grosbach
405e213008
ARM a few more VMUL implied destination operand form aliases.
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llvm-svn: 146177
2011-12-08 20:42:35 +00:00
Jim Grosbach
e1fe053f6e
ARM NEON two-operand aliases for VSHL(immediate).
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llvm-svn: 146125
2011-12-08 01:30:04 +00:00
Jim Grosbach
3e9384b103
ARM NEON two-operand aliases for VSHL(register).
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llvm-svn: 146123
2011-12-08 01:12:35 +00:00
Jim Grosbach
3b4d5c0510
ARM optional destination operand variants for VEXT instructions.
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llvm-svn: 146114
2011-12-08 00:43:47 +00:00
Jim Grosbach
0c64182f7c
Tidy up.
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llvm-svn: 146113
2011-12-08 00:41:54 +00:00
Jim Grosbach
c1cf417595
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
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llvm-svn: 146111
2011-12-08 00:31:07 +00:00
Jim Grosbach
6146f79b7d
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
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For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
Jim Grosbach
dd3788b044
ARM two-operand aliases for VAND/VEOR/VORR instructions.
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llvm-svn: 146095
2011-12-07 23:08:12 +00:00