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9191 Commits

Author SHA1 Message Date
Evan Cheng
88726d85eb Encode misc arithmetic instructions. 
llvm-svn: 58828
 2008-11-07 01:41:35 +00:00
Evan Cheng
3bcb71912f Encode extend instructions; more clean up. 
llvm-svn: 58818
 2008-11-06 22:15:19 +00:00
Evan Cheng
af54e4ed18 - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm. 
- Consolidate instruction formats.
- Other clean up.

llvm-svn: 58808
 2008-11-06 17:48:05 +00:00
Evan Cheng
aa24d19533 Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. 
llvm-svn: 58800
 2008-11-06 08:47:38 +00:00
Mon P Wang
41f90a3ee5 Widening cleanup 
llvm-svn: 58796
 2008-11-06 05:31:54 +00:00
Evan Cheng
078361bddc Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>. 
llvm-svn: 58793
 2008-11-06 03:35:07 +00:00
Evan Cheng
058721d10b Fix so_imm encoding bug; add support for MOVi2pieces. 
llvm-svn: 58790
 2008-11-06 02:25:39 +00:00
Evan Cheng
ca6759021b Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls. 
llvm-svn: 58789
 2008-11-06 01:21:28 +00:00
Evan Cheng
ce97712aa6 Encode pic load / store instructions; fix some encoding bugs. 
llvm-svn: 58780
 2008-11-05 23:22:34 +00:00
Evan Cheng
9970c31dcf Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions. 
llvm-svn: 58764
 2008-11-05 18:35:52 +00:00
Dan Gohman
1db84e57c5 Reintroduce a comment that was removed with the AddToISelQueue 
changes.

llvm-svn: 58760
 2008-11-05 17:16:24 +00:00
Richard Osborne
efd7edc731 Test commit, add Makefile for XCore target, more to follow. 
llvm-svn: 58755
 2008-11-05 09:53:58 +00:00
Evan Cheng
1378d6c7a9 Add more vector move low and zero-extend patterns. 
llvm-svn: 58752
 2008-11-05 06:04:51 +00:00
Evan Cheng
fdd6d65e39 Indentation. 
llvm-svn: 58750
 2008-11-05 06:03:38 +00:00
Dan Gohman
cd4b68bee9 Eliminate the ISel priority queue, which used the topological order for a 
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.

The impact on most targets is that AddToISelQueue calls can be simply removed.

In the x86 target, there are two additional notable changes.

The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.

Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.

llvm-svn: 58748
 2008-11-05 04:14:16 +00:00
Dan Gohman
215587186e Use getTargetConstant instead of getConstant for nodes that should not be visited 
by isel and potentially forced into registers.

llvm-svn: 58747
 2008-11-05 02:06:09 +00:00
Evan Cheng
2702e22b83 Rename isGVLazyPtr to isGVNonLazyPtr relocation. This represents Mac OS X 
indirect gv reference. Please don't call it lazy.

llvm-svn: 58746
 2008-11-05 01:50:32 +00:00
Evan Cheng
59112bc108 Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls. 
llvm-svn: 58725
 2008-11-04 22:19:55 +00:00
Evan Cheng
45496b349f Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes. 
llvm-svn: 58714
 2008-11-04 19:57:48 +00:00
Evan Cheng
d63b7563b7 Debug output tweak. 
llvm-svn: 58708
 2008-11-04 17:58:53 +00:00
Evan Cheng
088f7c51a4 LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR. 
llvm-svn: 58707
 2008-11-04 17:57:07 +00:00
Evan Cheng
28e234a959 For some targets, it's not possible to place GVs in the same memory buffer as the MachineCodeEmitter allocated memory. Code and data has different read / write / execution privilege requirements. 
This is a short term workaround. The current solution is for the JIT memory manager to manage code and data memory separately.

llvm-svn: 58688
 2008-11-04 09:30:48 +00:00
Evan Cheng
f15a9cfb31 Stylistic change. 
llvm-svn: 58683
 2008-11-04 06:10:06 +00:00
Evan Cheng
f117632c3f Handle ARM machine constantpool entries. 
llvm-svn: 58671
 2008-11-04 00:50:32 +00:00
Dan Gohman
0ba8aad1af The ANDMask node folds to a constant, and isn't the node that needs to 
have its node id set. The new and and shift nodes are the nodes that need
the IDs. This fixes PR2982.

llvm-svn: 58655
 2008-11-03 23:43:55 +00:00
Evan Cheng
999398c004 Remove a dead switch statement. 
llvm-svn: 58644
 2008-11-03 21:26:52 +00:00
Evan Cheng
b3fd30ed7c Minor code restructuring. No functionality change. 
llvm-svn: 58643
 2008-11-03 21:02:39 +00:00
Jim Grosbach
5262898365 Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there. 
llvm-svn: 58626
 2008-11-03 18:38:31 +00:00
Dan Gohman
155df8a79e Refactor various TargetAsmInfo subclasses' TargetMachine members away 
adding a TargetMachine member to the base TargetAsmInfo class instead.

llvm-svn: 58624
 2008-11-03 18:22:42 +00:00
Bill Wendling
c4e34b42f3 Whitespace fixes. No functionality change. 
llvm-svn: 58539
 2008-10-31 21:26:08 +00:00
Evan Cheng
53d4b6531e Add comment. 
llvm-svn: 58533
 2008-10-31 19:56:03 +00:00
Evan Cheng
07f57f0e41 Use better data structure for ConstPoolId2AddrMap. 
llvm-svn: 58532
 2008-10-31 19:55:13 +00:00
Evan Cheng
31306c546f Actually make debug output understandable. 
llvm-svn: 58529
 2008-10-31 19:15:52 +00:00
Mon P Wang
6363e90277 x86_64 rip-relative and magic mode address 
llvm-svn: 58528
 2008-10-31 19:13:42 +00:00
Evan Cheng
6a824a7741 Forgot this in last commit. 
llvm-svn: 58527
 2008-10-31 19:11:09 +00:00
Evan Cheng
afe2deb372 Encode PICADD; some code clean up. 
llvm-svn: 58526
 2008-10-31 19:10:44 +00:00
Bill Wendling
f8f6ed82f1 Revert r58489. It isn't correct for all cases. 
llvm-svn: 58523
 2008-10-31 18:30:19 +00:00
Evan Cheng
168bd3be1b Change x86 register allocation ordering to match that of gcc. Otherwise some tools get confused by prologue generated by llvm. 
llvm-svn: 58517
 2008-10-31 16:52:57 +00:00
Bill Wendling
0f1f4f8bb1 Don't skip over all "terminator" instructions when determining where to put the 
callee-saved restore code. It could skip over conditional jumps
accidentally. Instead, just skip the "return" instructions.

llvm-svn: 58489
 2008-10-31 04:00:23 +00:00
Dan Gohman
481e1fd0a6 Use MOVSSmr instead of EXTRACTPSmr in the case of extracting 
vector element 0 for a store, as it's smaller and faster.

llvm-svn: 58483
 2008-10-31 00:57:24 +00:00
Evan Cheng
56f4944f9a I think we got non-machine specific constpool entries covered. 
llvm-svn: 58474
 2008-10-30 23:43:36 +00:00
Duncan Sands
720e5548cb Shift amounts should have type getShiftAmountTy 
(i32 for PPC, not i8).  Correct this, and some
formatting while there.

llvm-svn: 58451
 2008-10-30 19:28:32 +00:00
Duncan Sands
ae31c14963 Shift amounts should have the type given by 
getShiftAmountTy (i32 in the case of CellSPU).

llvm-svn: 58449
 2008-10-30 19:24:28 +00:00
Evan Cheng
6f41528b91 ARM JIT should observe -relocation-model command line option. 
llvm-svn: 58433
 2008-10-30 16:10:54 +00:00
Mon P Wang
d7e34cd378 Add initial support for vector widening. Logic is set to widen for X86. 
One will only see an effect if legalizetype is not active.  Will move
support to LegalizeType soon.

llvm-svn: 58426
 2008-10-30 08:01:45 +00:00
Scott Michel
5b588212d8 Resolve bug 2947: vararg-marked functions must spill registers R3-R79 to stack 
so that va_start/va_arg/et.al. will walk arguments correctly for Cell SPU.

N.B.: Because neither clang nor llvm-gcc-4.2 can be built for CellSPU, this is
still unexorcised code.

llvm-svn: 58415
 2008-10-30 01:51:48 +00:00
Evan Cheng
69c2588244 Correct way to handle CONSTPOOL_ENTRY instructions. 
llvm-svn: 58409
 2008-10-29 23:55:43 +00:00
Evan Cheng
5e8fa6ef36 Add debugging support. 
llvm-svn: 58408
 2008-10-29 23:55:17 +00:00
Nate Begeman
e621f0539e Fix PEXTRQ encoding 
llvm-svn: 58403
 2008-10-29 23:07:17 +00:00
Dale Johannesen
ff738e8897 Add a RM pseudoreg for the rounding mode, which 
allows ppcf128->int conversion to work with
DeadInstructionElimination.  This is now turned
off but RM is harmless.  It does not do a complete
job of modeling the rounding mode.

Revert marking MFCR as using all 7 CR subregisters;
while correct, this caused the problem in PR 2964,
plus the local RA crash noted in the comments.
This was needed to make DeadInstructionElimination,
but as we are not running that, it is backed out
for now.  Eventually it should go back in and the
other problems fixed where they're broken.

llvm-svn: 58391
 2008-10-29 18:26:45 +00:00