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e009249ae1
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1291 Commits

Author SHA1 Message Date
Chris Lattner
e009249ae1 Fix a bug in merged condition handling (CodeGen/Generic/2006-10-27-CondFolding.ll). 
Add many fewer CFG edges and PHI node entries.  If there is a switch which has
the same block as multiple destinations, only add that block once as a successor/phi
node (in the jumptable case)

llvm-svn: 31242
 2006-10-27 23:50:33 +00:00
Jim Laskey
ef56bc9680 Switch over from SelectionNodeCSEMap to FoldingSet. 
llvm-svn: 31240
 2006-10-27 23:46:08 +00:00
Chris Lattner
e2297cd5a6 remove debug code 
llvm-svn: 31233
 2006-10-27 21:58:03 +00:00
Chris Lattner
0fab97080c Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to: 
cmpwi cr0, r4, 4
        bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
        cmplwi cr0, r3, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

instead of:

        cmpwi cr7, r4, 4
        mfcr r2
        addic r4, r3, -1
        subfe r3, r4, r3
        rlwinm r2, r2, 30, 31, 31
        or r2, r2, r3
        cmplwi cr0, r2, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true

llvm-svn: 31232
 2006-10-27 21:54:23 +00:00
Chris Lattner
05159debc4 Turn conditions like x<Y|z==q into multiple blocks. 
This compiles Regression/CodeGen/X86/or-branch.ll into:

_foo:
        subl $12, %esp
        call L_bar$stub
        movl 20(%esp), %eax
        movl 16(%esp), %ecx
        cmpl $5, %eax
        jl LBB1_1       #cond_true
LBB1_3: #entry
        testl %ecx, %ecx
        jne LBB1_2      #UnifiedReturnBlock
LBB1_1: #cond_true
        call L_bar$stub
        addl $12, %esp
        ret
LBB1_2: #UnifiedReturnBlock
        addl $12, %esp
        ret

instead of:

_foo:
        subl $12, %esp
        call L_bar$stub
        movl 20(%esp), %eax
        movl 16(%esp), %ecx
        cmpl $4, %eax
        setg %al
        testl %ecx, %ecx
        setne %cl
        testb %cl, %al
        jne LBB1_2      #UnifiedReturnBlock
LBB1_1: #cond_true
        call L_bar$stub
        addl $12, %esp
        ret
LBB1_2: #UnifiedReturnBlock
        addl $12, %esp
        ret

And on ppc to:

        cmpwi cr0, r29, 5
        blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
        cmplwi cr0, r30, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

instead of:

        cmpwi cr7, r4, 4
        mfcr r2
        addic r4, r3, -1
        subfe r30, r4, r3
        rlwinm r29, r2, 30, 31, 31
        and r2, r29, r30
        cmplwi cr0, r2, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

llvm-svn: 31230
 2006-10-27 21:36:01 +00:00
Evan Cheng
88c050f772 getPreIndexedLoad -> getIndexedLoad. 
llvm-svn: 31209
 2006-10-26 21:53:40 +00:00
Reid Spencer
6833ffe8b8 For PR950: 
Make necessary changes to support DIV -> [SUF]Div. This changes llvm to
have three division instructions: signed, unsigned, floating point. The
bytecode and assembler are bacwards compatible, however.

llvm-svn: 31195
 2006-10-26 06:15:43 +00:00
Chris Lattner
a797dd393f visitSwitchCase knows how to insert conditional branches well. Change 
visitBr to just call visitSwitchCase, eliminating duplicate logic.

llvm-svn: 31167
 2006-10-24 18:07:37 +00:00
Chris Lattner
79a1ca0a61 Generalize CaseBlock a bit more: 
Rename LHSBB/RHSBB to TrueBB/FalseBB.  Allow the RHS value to be null,
in which case the LHS is treated as a bool.

llvm-svn: 31166
 2006-10-24 17:57:59 +00:00
Chris Lattner
fc8e70297e generalize 'CaseBlock'. It really allows any comparison to be inserted. 
llvm-svn: 31161
 2006-10-24 17:03:35 +00:00
Chris Lattner
06236f7928 Minor tweak. Instead of generating: 
movl 32(%esp), %eax
        cmpl $1, %eax
        je LBB1_1       #bb
LBB1_4: #entry
        cmpl $2, %eax
        je LBB1_2       #bb2
        jmp LBB1_3      #UnifiedReturnBlock
LBB1_1: #bb

notice that we would miss the fall through and emit this instead:

        movl 32(%esp), %eax
        cmpl $2, %eax
        je LBB1_2       #bb2
LBB1_4: #entry
        cmpl $1, %eax
        jne LBB1_3      #UnifiedReturnBlock
LBB1_1: #bb

llvm-svn: 31130
 2006-10-23 18:38:22 +00:00
Chris Lattner
d91d082100 Fix phi node updating for switches lowered to linear sequences of branches. 
llvm-svn: 31125
 2006-10-22 23:00:53 +00:00
Chris Lattner
f592f04e3f disable this code for now, it's not yet safely updating phi nodes 
llvm-svn: 31124
 2006-10-22 22:47:10 +00:00
Chris Lattner
a07b38f113 Implement PR964 and Regression/CodeGen/Generic/SwitchLowering.ll 
llvm-svn: 31119
 2006-10-22 21:36:53 +00:00
Chris Lattner
2f54afc364 Make flag and chain edges visually distinguishable from value edges in DOT 
output.

llvm-svn: 31067
 2006-10-20 18:06:09 +00:00
Reid Spencer
d414793dbc For PR950: 
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.

llvm-svn: 31063
 2006-10-20 07:07:24 +00:00
Bill Wendling
edce5ede57 Partially in response to PR926: insert the newly created machine basic 
blocks into the basic block list when lowering the switch inst. into a
binary tree of if-then statements. This allows the "visitSwitchCase" func
to allow for fall-through behavior.

llvm-svn: 31057
 2006-10-19 21:46:38 +00:00
Jim Laskey
c06a0bc853 Add option for controlling inclusion of global AA. 
llvm-svn: 31040
 2006-10-18 19:08:31 +00:00
Jim Laskey
288c230cbd Use global info for alias analysis. 
llvm-svn: 31035
 2006-10-18 12:29:57 +00:00
Chris Lattner
8708a62f93 Trivial patch to speed up legalizing common i64 constants. 
llvm-svn: 31020
 2006-10-17 21:47:13 +00:00
Chris Lattner
bfbb76e103 Fix CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll 
llvm-svn: 31019
 2006-10-17 21:24:15 +00:00
Evan Cheng
3be6b15cd9 Fix printer for StoreSDNode. 
llvm-svn: 31017
 2006-10-17 21:18:26 +00:00
Evan Cheng
2113bdf34d Reflect MemOpAddrMode change; added a helper to create pre-indexed load. 
llvm-svn: 31016
 2006-10-17 21:14:32 +00:00
Jim Laskey
7f16ca4872 Make it simplier to dump DAGs while in DAGCombiner. Remove a nasty optimization. 
llvm-svn: 31009
 2006-10-17 19:33:52 +00:00
Evan Cheng
d9bec725a2 Make sure operand does have size and element type operands. 
llvm-svn: 30999
 2006-10-17 17:06:35 +00:00
Evan Cheng
2d9318cff1 Be careful when looking through a vbit_convert. Optimizing this: 
(vector_shuffle
  (vbitconvert (vbuildvector (copyfromreg v4f32), 1, v4f32), 4, f32),
  (undef, undef, undef, undef), (0, 0, 0, 0), 4, f32)
to the
  vbitconvert
is a very bad idea.

llvm-svn: 30989
 2006-10-16 22:49:37 +00:00
Jim Laskey
06f4428abc Pass AliasAnalysis thru to DAGCombiner. 
llvm-svn: 30984
 2006-10-16 20:52:31 +00:00
Jim Laskey
1070dfefba Tidy up after truncstore changes. 
llvm-svn: 30961
 2006-10-14 12:14:27 +00:00
Evan Cheng
bfd74c6d9c Debug tweak. 
llvm-svn: 30959
 2006-10-14 08:34:06 +00:00
Chris Lattner
08aa96b824 Make sure that the node returned by SimplifySetCC is added to the worklist 
so that it can be deleted if unused.

llvm-svn: 30955
 2006-10-14 03:52:46 +00:00
Chris Lattner
a515f322f3 fold setcc of a setcc. 
llvm-svn: 30953
 2006-10-14 01:02:29 +00:00
Chris Lattner
25ad62d132 When SimplifySetCC was moved to the DAGCombiner, it was never removed from 
SelectionDAG and it has since bitrotted.  Remove the copy from SelectionDAG.
Next, remove the constant folding piece of DAGCombiner::SimplifySetCC into
a new FoldSetCC method which can be used by getNode() and SimplifySetCC.

This fixes obscure bugs.

llvm-svn: 30952
 2006-10-14 00:41:01 +00:00
Jim Laskey
bf50140aac Reduce the workload by not adding chain users to work list. 
llvm-svn: 30948
 2006-10-13 23:32:28 +00:00
Chris Lattner
9b1878a28c Fix a bug where we incorrectly turned '(X & 0) == 0' into '(X & 0) >> -1', 
which is undefined.  "0" isn't a power of 2.

llvm-svn: 30947
 2006-10-13 22:46:18 +00:00
Evan Cheng
fe5bb5dbe6 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
llvm-svn: 30945
 2006-10-13 21:14:26 +00:00
Chris Lattner
70444d5663 Lower X%C into X/C+stuff. This allows the 'division by a constant' logic to 
apply to rems as well as divs.  This fixes PR945 and speeds up ReedSolomon
from 14.57s to 10.90s (which is now faster than gcc).

It compiles CodeGen/X86/rem.ll into:

_test1:
        subl $4, %esp
        movl %esi, (%esp)
        movl $2155905153, %ecx
        movl 8(%esp), %esi
        movl %esi, %eax
        imull %ecx
        addl %esi, %edx
        movl %edx, %eax
        shrl $31, %eax
        sarl $7, %edx
        addl %eax, %edx
        imull $255, %edx, %eax
        subl %eax, %esi
        movl %esi, %eax
        movl (%esp), %esi
        addl $4, %esp
        ret
_test2:
        movl 4(%esp), %eax
        movl %eax, %ecx
        sarl $31, %ecx
        shrl $24, %ecx
        addl %eax, %ecx
        andl $4294967040, %ecx
        subl %ecx, %eax
        ret
_test3:
        subl $4, %esp
        movl %esi, (%esp)
        movl $2155905153, %ecx
        movl 8(%esp), %esi
        movl %esi, %eax
        mull %ecx
        shrl $7, %edx
        imull $255, %edx, %eax
        subl %eax, %esi
        movl %esi, %eax
        movl (%esp), %esi
        addl $4, %esp
        ret

instead of div/idiv instructions.

llvm-svn: 30920
 2006-10-12 20:58:32 +00:00
Evan Cheng
61afb767eb Add RemoveDeadNode to remove a dead node and its (potentially) dead operands. 
llvm-svn: 30916
 2006-10-12 20:34:05 +00:00
Chris Lattner
e38ce54cc9 add a minor dag combine noticed when looking at PR945 
llvm-svn: 30915
 2006-10-12 20:23:19 +00:00
Jim Laskey
388c9681ef D'oh - need to use the rigth kind of store. 
llvm-svn: 30903
 2006-10-12 15:22:24 +00:00
Jim Laskey
eba756c1a7 Alias analysis of TRUNCSTORE. 
llvm-svn: 30889
 2006-10-11 18:55:16 +00:00
Jim Laskey
6efcd15c88 Typo 
llvm-svn: 30884
 2006-10-11 17:52:19 +00:00
Jim Laskey
4791a4ad14 Handle aliasing of loadext. 
llvm-svn: 30883
 2006-10-11 17:47:52 +00:00
Jim Laskey
fd6218f8f5 Fix regression in combiner alias analysis. 
llvm-svn: 30880
 2006-10-11 13:47:09 +00:00
Evan Cheng
9b31a4d4ed Naming consistency. 
llvm-svn: 30878
 2006-10-11 07:10:22 +00:00
Andrew Lenharth
4b783303e5 Jimptables working again on alpha. 
As a bonus, use the GOT node instead of the AlphaISD::GOT for internal stuff.

llvm-svn: 30873
 2006-10-11 04:29:42 +00:00
Chris Lattner
aa1741fc87 add two helper methods. 
llvm-svn: 30869
 2006-10-11 03:58:02 +00:00
Evan Cheng
d6b419ecb0 FindModifiedNodeSlot needs to add LoadSDNode ivars to create proper SelectionDAGCSEMap ID. 
llvm-svn: 30866
 2006-10-11 01:47:58 +00:00
Evan Cheng
0d8a340a8f Also update getNodeLabel for LoadSDNode. 
llvm-svn: 30861
 2006-10-10 20:11:26 +00:00
Evan Cheng
a12747d2b4 SDNode::dump should also print out extension type and VT. 
llvm-svn: 30860
 2006-10-10 20:05:10 +00:00
Chris Lattner
e0734f522f Fix another bug in extload promotion. 
llvm-svn: 30857
 2006-10-10 18:54:19 +00:00