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Commit Graph

128065 Commits

Author SHA1 Message Date
Duncan P. N. Exon Smith
e17ffed662 CodeGen: Remove an iterator => pointer conversion, NFC
Part of PR26753.

llvm-svn: 262154
2016-02-27 20:27:44 +00:00
Matt Arsenault
cd69621a21 AMDGPU: More bits of frame index are known to be zero
The maximum private allocation for the whole GPU is 4G,
so the maximum possible index for a single workitem is the
maximum size divided by the smallest granularity for a dispatch.

This increases the number of known zero high bits, which
enables more offset folding. The maximum private size per
workitem with this is 128M but may be smaller still.

llvm-svn: 262153
2016-02-27 20:26:57 +00:00
Duncan P. N. Exon Smith
eedb835102 CodeGen: Use MachineInstr& in InlineSpiller::rematerializeFor()
InlineSpiller::rematerializeFor() never uses its parameter as an
iterator, so take it by reference instead.  This removes an implicit
conversion from MachineBasicBlock::iterator to MachineInstr*.

llvm-svn: 262152
2016-02-27 20:23:14 +00:00
Duncan P. N. Exon Smith
9639cd8d5d CodeGen: Update LiveIntervalAnalysis API to use MachineInstr&, NFC
These parameters aren't expected to be null, so take them by reference.

llvm-svn: 262151
2016-02-27 20:14:29 +00:00
Duncan P. N. Exon Smith
779625a4a6 CodeGen: Change MachineInstr to use MachineInstr&, NFC
Change MachineInstr API to prefer MachineInstr& over MachineInstr*
whenever the parameter is expected to be non-null.  Slowly inching
toward being able to fix PR26753.

llvm-svn: 262149
2016-02-27 20:01:33 +00:00
Matt Arsenault
71c5d5fa5f DAGCombiner: Don't unnecessarily swap operands in ReassociateOps
In the case where op = add, y = base_ptr, and x = offset, this
transform:

(op y, (op x, c1)) -> (op (op x, y), c1)

breaks the canonical form of add by putting the base pointer in the
second operand and the offset in the first.

This fix is important for the R600 target, because for some address
spaces the base pointer and the offset are stored in separate register
classes. The old pattern caused the ISel code for matching addressing
modes to put the base pointer and offset in the wrong register classes,
which required no-trivial code transformations to fix.

llvm-svn: 262148
2016-02-27 19:57:45 +00:00
Duncan P. N. Exon Smith
cf94a78af2 CodeGen: Use MachineInstr& in HashMachineInstr, NFC
Also update HashEndOfMBB to take MachineBasicBlock&.

llvm-svn: 262146
2016-02-27 19:48:01 +00:00
Duncan P. N. Exon Smith
7318a4f23e CodeGen: Use MachineInstr& in AntiDepBreaker API, NFC
Take parameters as MachineInstr& instead of MachineInstr* in
AntiDepBreaker API, since these are required to be non-null.  No
functionality change intended.  Looking toward PR26753.

llvm-svn: 262145
2016-02-27 19:33:37 +00:00
Duncan P. N. Exon Smith
b415d051e7 CodeGen: Assert valid MI in AntiDepBreaker::UpdateDbgValue
This already assumes a valid MI, since it dereferences the MI in an
assertion before checking for null.  At an explicit assert.

llvm-svn: 262144
2016-02-27 19:23:34 +00:00
Duncan P. N. Exon Smith
906424d422 AArch64: Use MachineInstr& in guaranteesZeroRegInBlock(), NFC
llvm-svn: 262143
2016-02-27 19:12:54 +00:00
Duncan P. N. Exon Smith
b131d0efa2 CodeGen: Update DFAPacketizer API to take MachineInstr&, NFC
In all but one case, change the DFAPacketizer API to take MachineInstr&
instead of MachineInstr*.  In DFAPacketizer::endPacket(), take
MachineBasicBlock::iterator.  Besides cleaning up the API, this is in
search of PR26753.

llvm-svn: 262142
2016-02-27 19:09:00 +00:00
Duncan P. N. Exon Smith
5aed8db9e7 WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC
Update APIs in MachineInstrBundle.h to take and return MachineInstr&
instead of MachineInstr* when the instruction cannot be null.  Besides
being a nice cleanup, this is tacking toward a fix for PR26753.

llvm-svn: 262141
2016-02-27 17:05:33 +00:00
JF Bastien
58b3415c80 WebAssembly: fix build
It was broken by the work for PR26753.

llvm-svn: 262140
2016-02-27 16:38:23 +00:00
Renato Golin
e3031ad0db Revert "[sancov] do not instrument nodes that are full pre-dominators"
This reverts commit r262103, as it broke all ARM and AArch64 bots.

llvm-svn: 262139
2016-02-27 14:19:19 +00:00
Simon Pilgrim
1ad94fd8a6 Tidyup for loops - don't repeat upper limit evaluation if you don't have to. NFCI.
llvm-svn: 262137
2016-02-27 13:26:58 +00:00
Chris Dewhurst
3bd9485a7c Addition of tests to previous check-in. Tests for coprocessor register usage in Sparc.
Previous check-in message was:

The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual.
These are all co-processor registers, with the exception of the floating-point deferred-trap queue register.
Although these will not be lowered automatically by any instructions, it allows the use of co-processor
instructions implemented by inline-assembly.

Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td,
which was formerly causing a problem in the disassembly of the %fq register.

llvm-svn: 262135
2016-02-27 12:52:26 +00:00
Simon Pilgrim
d92b022fab [X86][AVX] vpermilvar.pd mask element indices only use bit1
llvm-svn: 262134
2016-02-27 12:51:46 +00:00
Chris Dewhurst
7df4542eb7 The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual.
These are all co-processor registers, with the exception of the floating-point deferred-trap queue register.
Although these will not be lowered automatically by any instructions, it allows the use of co-processor
instructions implemented by inline-assembly.

Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td,
which was formerly causing a problem in the disassembly of the %fq register.

llvm-svn: 262133
2016-02-27 12:49:59 +00:00
Simon Pilgrim
bf512bbe9a [X86][AVX] Added AVX1 target shuffle combine tests
llvm-svn: 262132
2016-02-27 12:33:08 +00:00
Simon Pilgrim
5490389df9 Strip trailing whitespace. NFCI.
llvm-svn: 262131
2016-02-27 11:49:16 +00:00
Chandler Carruth
b38ca77e0f [PM] Loosen the regex for the proxy template name even further to cope
with 'class' keywords in the template arguments and other silliness.

llvm-svn: 262130
2016-02-27 11:07:16 +00:00
Chandler Carruth
634330d245 [PM] Use a boring regex instead of explicitly naming the analysis
manager as some compilers print the typedef name and others print the
"canonical" name of the underlying class template.

This isn't really an important artifact of the test anyways so it seems
fine to just loosen the test assertions here.

llvm-svn: 262129
2016-02-27 10:48:14 +00:00
Chandler Carruth
c784a0ee88 [PM] Provide explicit instantiation declarations and definitions for the
PassManager and AnalysisManager template specializations as well.

llvm-svn: 262128
2016-02-27 10:45:35 +00:00
Chandler Carruth
532f5864dc [PM] Provide two templates for the two directionalities of analysis
manager proxies and use those rather than repeating their definition
four times.

There are real differences between the two directions: outer AMs are
const and don't need to have invalidation tracked. But every proxy in
a particular direction is identical except for the analysis manager type
and the IR unit they proxy into. This makes them prime candidates for
nice templates.

I've started introducing explicit template instantiation declarations
and definitions as well because we really shouldn't be emitting all this
everywhere. I'm going to go back and add the same for the other
templates like this in a follow-up patch.

I've left the analysis manager as an opaque type rather than using two
IR units and requiring it to be an AnalysisManager template
specialization. I think its important that users retain the ability to
provide their own custom analysis management layer and provided it has
the appropriate API everything should Just Work.

llvm-svn: 262127
2016-02-27 10:38:10 +00:00
Matt Arsenault
a8505608a7 DAGCombiner: Relax sqrt NaN folding check
This is OK for +0 since compares to +/-0 give the same result.

llvm-svn: 262125
2016-02-27 09:38:05 +00:00
Matt Arsenault
6ecfce9ba2 AMDGPU: Split vi-insts subtarget feature
This will be more useful for marking builtins acceptable for which
subtargets.

llvm-svn: 262121
2016-02-27 08:53:55 +00:00
Matt Arsenault
7522feaa7e AMDGPU: Add s_sleep intrinsic
llvm-svn: 262120
2016-02-27 08:53:52 +00:00
Matt Arsenault
1bcd37150d AMDGPU: Implement readcyclecounter
This matches the behavior of the HSAIL clock instruction.
s_realmemtime is used if the subtarget supports it, and falls
back to s_memtime if not.

Also introduces new intrinsics for each of s_memtime / s_memrealtime.

llvm-svn: 262119
2016-02-27 08:53:46 +00:00
Duncan P. N. Exon Smith
9bc441714a CodeGen: Avoid implicit conversion in MachineInstrBuilder, NFC
Avoid another implicit conversion from MachineInstrBundleIterator to
MachineInstr*, this time in MachineInstrBuilder.h (this is in pursuit of
PR26753).

llvm-svn: 262118
2016-02-27 07:00:35 +00:00
Duncan P. N. Exon Smith
be21e15f72 CodeGen: Remove implicit iterator to pointer conversions, NFC
Remove a couple of implicit conversions from MachineInstrBundleIterator
to MachineInstr*.

llvm-svn: 262116
2016-02-27 06:51:00 +00:00
Duncan P. N. Exon Smith
13c519204e CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC
Take MachineInstr by reference instead of by pointer in SlotIndexes and
the SlotIndex wrappers in LiveIntervals.  The MachineInstrs here are
never null, so this cleans up the API a bit.  It also incidentally
removes a few implicit conversions from MachineInstrBundleIterator to
MachineInstr* (see PR26753).

At a couple of call sites it was convenient to convert to a range-based
for loop over MachineBasicBlock::instr_begin/instr_end, so I added
MachineBasicBlock::instrs.

llvm-svn: 262115
2016-02-27 06:40:41 +00:00
Sean Silva
460bbafe5e [instrprof] Use __{start,stop}_SECNAME on PS4 too.
Summary:
The PS4 linker seems to handle this fine.

Hi David, it seems that indeed most ELF linkers support
__{start,stop}_SECNAME, as our proprietary linker does as well.

This follows the pattern of r250679 w.r.t. the testing.

Maggie, Phillip, Paul: I've tested this with the PS4 SDK 3.5 toolchain
prerelease and it seems to work fine.

Reviewers: davidxl

Subscribers: probinson, phillip.power, MaggieYi

Differential Revision: http://reviews.llvm.org/D17672

llvm-svn: 262112
2016-02-27 06:01:26 +00:00
Mike Aizatsky
5bc3e758d6 [sancov] properly initializing pass.
llvm-svn: 262111
2016-02-27 05:50:40 +00:00
Kostya Serebryany
2e7a6d59f7 [libFuzzer] don't emit callbacks to sanitizer run-time in -fsanitize-coverage=trace-pc mode; update libFuzzer doc for previous commit
llvm-svn: 262110
2016-02-27 05:45:12 +00:00
Philip Reames
bbfba6fb1c Suppress an uncovered switch warning [NFC]
llvm-svn: 262109
2016-02-27 05:18:30 +00:00
Chandler Carruth
4def732ecd [LICM] Teach LICM how to handle cases where the alias set tracker was
merged into a loop that was subsequently unrolled (or otherwise nuked).

In this case it can't merge in the ASTs for any remaining nested loops,
it needs to re-add their instructions dircetly.

The fix is very isolated, but I've pulled the code for merging blocks
into the AST into a single place in the process. The only behavior
change is in the case which would have crashed before.

This fixes a crash reported by Mikael Holmen on the list after r261316
restored much of the loop pass pipelining and allowed us to actually do
this kind of nested transformation sequenc. I've taken that test case
and further reduced it into the somewhat twisty maze of loops in the
included test case. This does in fact trigger the bug even in this
reduced form.

llvm-svn: 262108
2016-02-27 04:34:07 +00:00
Kostya Serebryany
33b6a19483 [libFuzzer] fixing the bot
llvm-svn: 262106
2016-02-27 03:14:23 +00:00
Mike Aizatsky
82adfc84dc [sancov] print_coverage_points command.
Differential Revision: http://reviews.llvm.org/D17670

llvm-svn: 262104
2016-02-27 02:21:44 +00:00
Mike Aizatsky
efd9fa98d1 [sancov] do not instrument nodes that are full pre-dominators
Summary:
Without tree pruning clang has 2,667,552 points.
Wiht only dominators pruning: 1,515,586.
With both dominators & predominators pruning: 1,340,534.

Differential Revision: http://reviews.llvm.org/D17671

llvm-svn: 262103
2016-02-27 02:10:27 +00:00
Kostya Serebryany
471f3a8bda [libFuzzer] speedup path coverage handling
llvm-svn: 262102
2016-02-27 01:50:16 +00:00
Junmo Park
8063e61895 Minor code cleanup. NFC.
llvm-svn: 262096
2016-02-27 01:10:43 +00:00
Reid Kleckner
43aeb743c9 [InstCombine] Be more conservative about removing stackrestore
We ended up removing a save/restore pair around an inalloca call,
leading to a miscompile in Chromium.

llvm-svn: 262095
2016-02-27 00:53:54 +00:00
Paul Robinson
c1ad81589f Revert r262092, caught LLD tests
llvm-svn: 262093
2016-02-26 23:44:10 +00:00
Paul Robinson
38a2b48139 [FileCheck] Abort if -NOT is combined with another suffix.
Combinations of suffixes that look useful actually are ignored;
complaining about them will avoid mistakes.

Differential Revision: http://reviews.llvm.org/D17587

llvm-svn: 262092
2016-02-26 23:34:02 +00:00
Cong Hou
1cb5dabaaa Fix a bug in isVectorReductionOp() in SelectionDAGBuilder.cpp that may cause assertion failure on AArch64.
llvm-svn: 262091
2016-02-26 23:25:30 +00:00
Ahmed Bougacha
19da25ce7b [X86] Move an encoding test from CodeGen to MC. NFC.
llvm-svn: 262089
2016-02-26 23:00:03 +00:00
Ahmed Bougacha
25bb079df3 [X86] Delete old redundant test. NFC.
llvm-svn: 262088
2016-02-26 23:00:00 +00:00
Ahmed Bougacha
f14633274b [X86] Fix a stale comment. NFC.
llvm-svn: 262087
2016-02-26 22:59:57 +00:00
Ahmed Bougacha
05e77f2852 [X86] Remove the unused SDTX86atomicBinary. NFC.
llvm-svn: 262086
2016-02-26 22:59:41 +00:00
Philip Reames
a3ddb00a03 [LVI] Extend select handling to catch min/max/clamp idioms
Most of this is fairly straight forward. Add handling for min/max via existing matcher utility and ConstantRange routines.  Add handling for clamp by exploiting condition constraints on inputs.  

Note that I'm only handling two constant ranges at this point. It would be reasonable to consider treating overdefined as a full range if the instruction is typed as an integer, but that should be a separate change.

Differential Revision: http://reviews.llvm.org/D17184

llvm-svn: 262085
2016-02-26 22:53:59 +00:00