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56 Commits

Author SHA1 Message Date
Matt Arsenault
e19ddbd0dc R600: Mostly remove remaining AMDIL intrinsics. 
Delete all unused ones, and add new AMDGPU named intrinsics for
the ones that are. Handle the old AMDIL names for comptability (although
remove their GCCBuiltin names) and add tests since there weren't any
for these before.

llvm-svn: 210827
 2014-06-12 21:15:44 +00:00
Matt Arsenault
a75d166beb R600/SI: Use v_cvt_f32_ubyte* instructions 
This eliminates extra extract instructions when loading an i8 vector to
a float vector.

llvm-svn: 210666
 2014-06-11 17:50:44 +00:00
Matt Arsenault
6728d3c17d R600: Add helper functions. 
Extract these from some of my other patches, since this
is the only thing really making them dependent on each other.

llvm-svn: 210627
 2014-06-11 03:29:54 +00:00
Matt Arsenault
4ab9246e99 R600: Implement ComputeNumSignBitsForTargetNode for BFE 
llvm-svn: 209460
 2014-05-22 18:09:03 +00:00
Matt Arsenault
e43426533f R600: Add intrinsics for mad24 
llvm-svn: 209456
 2014-05-22 18:00:15 +00:00
Matt Arsenault
cb883e1e39 Remove unused method declaration 
llvm-svn: 209174
 2014-05-19 22:55:35 +00:00
Jay Foad
e0eac700cb Rename ComputeMaskedBits to computeKnownBits. "Masked" has been 
inappropriate since it lost its Mask parameter in r154011.

llvm-svn: 208811
 2014-05-14 21:14:37 +00:00
Tom Stellard
83d3208148 R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine() 
llvm-svn: 208429
 2014-05-09 16:42:16 +00:00
Craig Topper
9900b9f93b [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition 
llvm-svn: 207503
 2014-04-29 07:57:24 +00:00
Matt Arsenault
f022fe68e4 R600: Emit error instead of unreachable on function call 
llvm-svn: 206904
 2014-04-22 16:42:00 +00:00
Matt Arsenault
de91105f57 R600: Minor cleanups. 
Fix indentation, better line wrapping, unused includes.

llvm-svn: 206562
 2014-04-18 07:40:20 +00:00
Matt Arsenault
65fde80ac6 Move ExtractVectorElements to SelectionDAG. 
This seems generally useful, and makes sense to
go along with SplitVector.

llvm-svn: 206041
 2014-04-11 17:47:30 +00:00
Tom Stellard
557024a30d R600: Match 24-bit arithmetic patterns in a Target DAGCombine 
Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.

This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched.  This occasionally
resulted in some instructions being incorrectly deleted from the
program.

v2:
  - Fix bug with 64-bit mul

llvm-svn: 205731
 2014-04-07 19:45:41 +00:00
Matt Arsenault
a8674ddad8 R600: Add target nodes for BFM and BFI 
llvm-svn: 205235
 2014-03-31 18:21:13 +00:00
Matt Arsenault
7f99777a74 R600: Implement isZExtFree. 
This allows 64-bit operations that are truncated to be reduced
to 32-bit ones.

llvm-svn: 204946
 2014-03-27 17:23:31 +00:00
Matt Arsenault
e42a0c31f3 R600/SI: Fix unreachable with a sext_in_reg to an illegal type. 
llvm-svn: 204945
 2014-03-27 17:23:24 +00:00
Matt Arsenault
63960a4cd8 R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp 
Remove handling of select_cc, since it makes no sense to be there. This
now does nothing, but I'll be adding some handling of other target nodes
soon.

llvm-svn: 204743
 2014-03-25 18:18:27 +00:00
Matt Arsenault
7ae7f52221 R600: Implement isNarrowingProfitable. 
llvm-svn: 204658
 2014-03-24 19:43:31 +00:00
Matt Arsenault
553297669c R600: Match sign_extend_inreg to BFE instructions 
llvm-svn: 204072
 2014-03-17 18:58:11 +00:00
Craig Topper
b0056a4ca7 Switch all uses of LLVM_OVERRIDE to just use 'override' directly. 
llvm-svn: 202621
 2014-03-02 09:09:27 +00:00
Matt Arsenault
a3de4dc001 R600/SI - Add new CI arithmetic instructions. 
Does not yet include larger part required
to match v_mad_i64_i32 / v_mad_u64_u32.

llvm-svn: 202077
 2014-02-24 21:01:28 +00:00
Benjamin Kramer
b51d0de00f R600: Always implement both versions of isTruncateFree and add a sanity check. 
llvm-svn: 201222
 2014-02-12 10:17:54 +00:00
Matt Arsenault
38609a2ae1 R600: Implement isTruncateFree 
Truncation is just accessing a subregister for any multiple of
the register size, so it's free.

llvm-svn: 201107
 2014-02-10 19:57:42 +00:00
Tom Stellard
d424fe57e4 R600: Add support for global addresses with constant initializers 
llvm-svn: 199825
 2014-01-22 19:24:21 +00:00
Tom Stellard
369c33de20 R600/SI: Add support for i8 and i16 private loads/stores 
llvm-svn: 199823
 2014-01-22 19:24:14 +00:00
Matt Arsenault
084675c776 Add target hook to prevent folding some bitcasted loads. 
This is to avoid this transformation in some cases:
fold (conv (load x)) -> (load (conv*)x)

On architectures that don't natively support some vector
loads efficiently casting the load to a smaller vector of
larger types and loading is more efficient.

Patch by Micah Villmow.

llvm-svn: 194783
 2013-11-15 04:42:23 +00:00
Tom Stellard
c38302be13 R600/SI: Add support for private address space load/store 
Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.

llvm-svn: 194626
 2013-11-13 23:36:50 +00:00
Tom Stellard
e058534e9a R600: Custom lower f32 = uint_to_fp i64 
llvm-svn: 193701
 2013-10-30 17:22:05 +00:00
Tom Stellard
2b6ff7e802 R600: Fix handling of vector kernel arguments 
The SelectionDAGBuilder was promoting vector kernel arguments to legal
types, but this won't work for R600 and SI since kernel arguments are
stored in memory and can't be promoted.  In order to handle vector
arguments correctly we need to look at the original types from the LLVM IR
function.

llvm-svn: 193215
 2013-10-23 00:44:32 +00:00
Tom Stellard
6a507da088 R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback 
For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist.

The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take
a resource descriptor might be nicer.

The maximum number of input SGPRs is bumped to 17.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 190575
 2013-09-12 02:55:14 +00:00
Tom Stellard
471cae1398 R600: Add support for vector local memory loads 
llvm-svn: 189226
 2013-08-26 15:06:04 +00:00
Tom Stellard
743d74f1b3 R600: Add support for v4i32 and v2i32 local stores 
llvm-svn: 189222
 2013-08-26 15:05:44 +00:00
Tom Stellard
c42a38e3ad R600: Add support for global vector stores with elements less than 32-bits 
Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 188520
 2013-08-16 01:12:11 +00:00
Tom Stellard
8d9a460dad R600: Add support for i16 and i8 global stores 
Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 188519
 2013-08-16 01:12:06 +00:00
Tom Stellard
0f3c885b1a R600/SI: Improve legalization of vector operations 
This should fix hangs in the OpenCL piglit tests.

llvm-svn: 188431
 2013-08-14 23:25:00 +00:00
Tom Stellard
d7b0828247 R600/SI: Convert v16i8 resource descriptors to i128 
Now that compute support is better on SI, we can't continue using v16i8
for descriptors since this is also a legal type in OpenCL.

This patch fixes numerous hangs with the piglit OpenCL test and since
we now use a target specific DAG node for LOAD_CONSTANT with the
correct MemOperandFlags, this should also fix:

https://bugs.freedesktop.org/show_bug.cgi?id=66805

llvm-svn: 188429
 2013-08-14 23:24:45 +00:00
Tom Stellard
a96032b0e7 R600: Implement TargetLowering::getVectorIdxTy() 
We use MVT::i32 for the vector index type, because we use 32-bit
operations to caculate offsets when dynamically indexing vectors.

llvm-svn: 187749
 2013-08-05 22:22:07 +00:00
Tom Stellard
cf58aac74c DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free 
This commit also implements these functions for R600 and removes a test
case that was relying on the buggy behavior.

llvm-svn: 187007
 2013-07-23 23:55:03 +00:00
Vincent Lejeune
d29844ad2e R600: Use DAG lowering pass to handle fcos/fsin 
NOTE: This is a candidate for the stable branch.
llvm-svn: 185940
 2013-07-09 15:03:11 +00:00
Tom Stellard
99f122e9be R600: Add local memory support via LDS 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 185162
 2013-06-28 15:47:08 +00:00
Tom Stellard
0c2bbb2a1f R600/SI: Add support for work item and work group intrinsics 
llvm-svn: 183138
 2013-06-03 17:40:18 +00:00
Tom Stellard
8e0ca8c4b9 R600/SI: Rework MUBUF store instructions 
The lowering of stores is now mostly handled in the tablegen files.  No
more BUFFER_STORE nodes I generated during legalization.

llvm-svn: 183130
 2013-06-03 17:39:37 +00:00
Andrew Trick
2790ee3a8e Track IR ordering of SelectionDAG nodes 2/4. 
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

llvm-svn: 182703
 2013-05-25 02:42:55 +00:00
Tom Stellard
5ca265d214 R600: Swap the legality of rotl and rotr 
The hardware supports rotr and not rotl.

llvm-svn: 182285
 2013-05-20 15:02:19 +00:00
Vincent Lejeune
152473c61c R600: Relax some vector constraints on Dot4. 
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.

llvm-svn: 182126
 2013-05-17 16:50:32 +00:00
Vincent Lejeune
0c663b698a R600: Improve texture handling 
llvm-svn: 182125
 2013-05-17 16:50:20 +00:00
Tom Stellard
8ad4f7c25b R600/SI: Add support for buffer stores v2 
v2:
  - Use the ADDR64 bit

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178931
 2013-04-05 23:31:51 +00:00
Christian Konig
b39290c18e R600/SI: add proper formal parameter handling for SI 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176623
 2013-03-07 09:03:52 +00:00
Christian Konig
c385dfd27c R600/SI: add folding helper 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176100
 2013-02-26 17:52:16 +00:00
Vincent Lejeune
9328de1e18 R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern 
llvm-svn: 175446
 2013-02-18 14:11:28 +00:00