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51653 Commits

Author SHA1 Message Date
Jim Grosbach
3352ab97ca ARM NEON VCLT(register) is a pseudo aliasing VCGT(register). 
llvm-svn: 146039
 2011-12-07 17:51:15 +00:00
Duncan Sands
8b1c4875c3 Remove unused include. 
llvm-svn: 146037
 2011-12-07 17:18:31 +00:00
Craig Topper
6b3cc1405f Fix a bunch of SSE/AVX patterns to use proper memop types. In particular, not using integer loads other than v2i64/v4i64 since the others are all promoted. 
llvm-svn: 146031
 2011-12-07 08:30:53 +00:00
Bill Wendling
4741665fb1 Adjust the stack by one pointer size for all frameless stacks. 
llvm-svn: 146030
 2011-12-07 07:58:55 +00:00
Bill Wendling
757cba38ba Fix off-by-one error when encoding the stack size for a frameless stack. 
llvm-svn: 146029
 2011-12-07 07:49:49 +00:00
Evan Cheng
1acd685d87 Add bundle aware API for querying instruction properties and switch the code 
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
 2011-12-07 07:15:52 +00:00
David Blaikie
4b898ea444 Adding missing anchor to DATDeltaAlgorithm. 
llvm-svn: 146025
 2011-12-07 06:44:23 +00:00
Hal Finkel
01f7c7a17e make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs 
llvm-svn: 146024
 2011-12-07 06:34:06 +00:00
Hal Finkel
604156e099 make base register selection used in eliminateFrameIndex 64-bit clean 
llvm-svn: 146023
 2011-12-07 06:34:02 +00:00
Hal Finkel
8589827358 set mayStore and mayLoad on CR pseudos 
llvm-svn: 146022
 2011-12-07 06:33:57 +00:00
Hal Finkel
fa3b46319d 64-bit LR8 load should use X11 not R11 
llvm-svn: 146021
 2011-12-07 06:32:37 +00:00
Jakob Stoklund Olesen
2f0e1e182f Eliminate delta argument from AdjustBBOffsetsAfter. 
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.

Eliminate one redundant AdjustBBOffsetsAfter call.

llvm-svn: 146018
 2011-12-07 05:17:30 +00:00
Jakob Stoklund Olesen
90c2c87a91 Compute some alignment information for each basic block. 
These fields are not used for anything yet.

llvm-svn: 146017
 2011-12-07 04:17:35 +00:00
Eli Friedman
e74e55c372 Zap unnecessary isIntDivCheap() check. PR11485. No testcase because this doesn't affect any in-tree target. 
llvm-svn: 146015
 2011-12-07 03:55:52 +00:00
Jim Grosbach
a740cc6bc9 ARM tidy up and remove no longer needed InstAlias definitions. 
The TokenAlias handling of data type suffices renders these unnecessary.

llvm-svn: 146010
 2011-12-07 01:50:36 +00:00
Jakob Stoklund Olesen
d3e5443796 Move common expression into a method. 
llvm-svn: 146008
 2011-12-07 01:22:52 +00:00
Jim Grosbach
19d37b966b ARM Implement ARM ARM Table A7-3 via TokenAlias. 
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.

rdar://10435076

llvm-svn: 146007
 2011-12-07 01:17:58 +00:00
Jakob Stoklund Olesen
a2d7f79da0 Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>. 
No functional change is intended.

llvm-svn: 146005
 2011-12-07 01:08:25 +00:00
Jakob Stoklund Olesen
c1f4115eb1 Add missing check. 
llvm-svn: 146004
 2011-12-07 01:08:22 +00:00
Jim Grosbach
57478f4961 ARM: NEON SHLL instruction immediate operand range checking. 
llvm-svn: 146003
 2011-12-07 01:07:24 +00:00
Eli Friedman
9e8d557cd1 Support vector bitcasts in the AsmPrinter. PR11495. 
llvm-svn: 146001
 2011-12-07 00:50:54 +00:00
Bruno Cardoso Lopes
d610f464bf Add a few moreLocal/Global R_MIPS_GOT related fixups and 
make the addend fixup code a bit more generic

Patch by Jack Carter.

llvm-svn: 145998
 2011-12-07 00:28:57 +00:00
Jakob Stoklund Olesen
e612fdbbab Add MachineOperand IsInternalRead flag. 
This flag is used when bundling machine instructions.  It indicates
whether the operand reads a value defined inside or outside its bundle.

llvm-svn: 145997
 2011-12-07 00:22:07 +00:00
Eli Friedman
5545db0906 Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves correctly. PR11494. 
llvm-svn: 145996
 2011-12-07 00:11:56 +00:00
Jakub Staszak
f1b60daf50 Remove unneeded type. 
llvm-svn: 145995
 2011-12-07 00:08:00 +00:00
Jim Grosbach
960e6c5a43 ARM: Parameterize the immediate operand type for NEON VSHLL. 
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.

llvm-svn: 145994
 2011-12-07 00:02:17 +00:00
Jakub Staszak
e4104abf3c - Remove unneeded #includes. 
- Remove unused types/fields.
- Add some constantness.

llvm-svn: 145993
 2011-12-06 23:59:33 +00:00
Jakob Stoklund Olesen
436d9f98e3 Revert r145971: "Use conservative size estimate for tBR_JTr." 
This caused more offset errors.

llvm-svn: 145980
 2011-12-06 22:41:31 +00:00
Bill Wendling
a4163dadb8 Re-enable compact unwind. It seems to work now. <rdar://problem/10441838> 
llvm-svn: 145977
 2011-12-06 22:18:12 +00:00
Bill Wendling
7380d4e412 Explicitly check for the different SUB instructions. 
llvm-svn: 145976
 2011-12-06 22:14:27 +00:00
Evan Cheng
5061553f9d First chunk of MachineInstr bundle support. 
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975
 2011-12-06 22:12:01 +00:00
Jakob Stoklund Olesen
c5e1f4a242 Use conservative size estimate for tBR_JTr. 
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.

It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.

llvm-svn: 145971
 2011-12-06 21:55:39 +00:00
Jakob Stoklund Olesen
e757462141 Remove alignment from deserted constant islands. 
ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.

This should fix the many Thumb1 assembler errors in the nightly test
suite.

The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.

<rdar://problem/10534709>

llvm-svn: 145970
 2011-12-06 21:55:35 +00:00
Bill Wendling
5fabb465e2 Encode the total stack if there isn't a frame. 
llvm-svn: 145969
 2011-12-06 21:34:01 +00:00
Bill Wendling
075cd4a296 * Add a macro to remove a magic number. 
* Rename variables to reflect what they're actually used for.

llvm-svn: 145968
 2011-12-06 21:23:42 +00:00
Jakob Stoklund Olesen
5fb70d560d Pretty-print basic block alignment. 
llvm-svn: 145965
 2011-12-06 21:08:39 +00:00
Hal Finkel
bf3ebfa211 add RESTORE_CR and support CR unspills 
llvm-svn: 145961
 2011-12-06 20:55:36 +00:00
Hal Finkel
a3483924a6 remove old FIXME 
llvm-svn: 145960
 2011-12-06 20:52:56 +00:00
Bill Wendling
9f248310fc Check the correct value for small stack sizes. Also modify some comments. 
llvm-svn: 145954
 2011-12-06 19:16:17 +00:00
Bill Wendling
5229d524ea For a small sized stack, we encode that value directly with no "stack adjust" value. 
llvm-svn: 145952
 2011-12-06 19:09:06 +00:00
Justin Holewinski
c9457b712c PTX: Continue to fix up the register mess. 
llvm-svn: 145947
 2011-12-06 17:39:48 +00:00
Justin Holewinski
f54a8af7f1 PTX: Encode registers as unsigned values in the MC asm printer instead of using external symbols 
llvm-svn: 145946
 2011-12-06 17:39:46 +00:00
Sebastian Pop
182ae6a6fa use space star instead of star space 
llvm-svn: 145944
 2011-12-06 17:34:16 +00:00
Sebastian Pop
cb55bb22ab add missing point at the end of sentences 
llvm-svn: 145943
 2011-12-06 17:34:11 +00:00
Benjamin Kramer
7df1659ad7 Simplify common predecessor finding. 
- Walking over pred_begin/pred_end is an expensive operation.
- PHINodes contain a value for each predecessor anyway.
- While it may look like we used to save a few iterations with the set,
  be aware that getIncomingValueForBlock does a linear search on
  the values of the phi node.
- Another -5% on ARMDisassembler.cpp (Release build). This was the last
  entry in the profile that was obviously wasting time.

llvm-svn: 145937
 2011-12-06 16:14:29 +00:00
Benjamin Kramer
933fd2afff Push StringRefs through the metadata interface. 
llvm-svn: 145934
 2011-12-06 11:50:26 +00:00
Craig Topper
26f41cda03 Add X86ISD::HADD/HSUB to getTargetNodeName 
llvm-svn: 145929
 2011-12-06 09:31:36 +00:00
Craig Topper
8b05e7d035 Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those. 
llvm-svn: 145927
 2011-12-06 09:04:59 +00:00
Craig Topper
846d53deed Merge floating point and integer UNPCK X86ISD node types. 
llvm-svn: 145926
 2011-12-06 08:21:25 +00:00
Craig Topper
e6e44c24dd Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs. 
llvm-svn: 145924
 2011-12-06 05:31:16 +00:00
Jim Grosbach
5b4f7d74de ARM mode 'mul' operand ordering tweak. 
Same as r145922, just for ARM mode.

llvm-svn: 145923
 2011-12-06 05:28:00 +00:00
Jim Grosbach
dc7d42f559 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

llvm-svn: 145922
 2011-12-06 05:03:45 +00:00
Craig Topper
72b41227d8 Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted. 
llvm-svn: 145921
 2011-12-06 04:59:07 +00:00
Jim Grosbach
8bdbe92631 Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

llvm-svn: 145919
 2011-12-06 04:49:29 +00:00
Bruno Cardoso Lopes
6739e47b15 Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter 
llvm-svn: 145912
 2011-12-06 03:34:48 +00:00
Bruno Cardoso Lopes
379e4c7a14 Explicit symbols for gnu mimicing relocations. Patch by Jack Carter 
llvm-svn: 145911
 2011-12-06 03:34:42 +00:00
Bruno Cardoso Lopes
4638d36bd2 Add register HWR29 numbering. Patch by Jack Carter 
llvm-svn: 145910
 2011-12-06 03:34:36 +00:00
Andrew Trick
04c98888bc LSR: prune undesirable formulae early. 
It's always good to prune early, but formulae that are unsatisfactory
in their own right need to be removed before running any other pruning
heuristics. We easily avoid generating such formulae, but we need them
as an intermediate basis for forming other good formulae.

llvm-svn: 145906
 2011-12-06 03:13:31 +00:00
Evan Cheng
91ae428cc0 Mix some minor misuse of MachineBasicBlock iterator. 
llvm-svn: 145903
 2011-12-06 02:49:06 +00:00
Pete Cooper
61ffb8fcc5 Removed isWinToJoinCrossClass from the register coalescer. 
The new register allocator is much more able to split back up ranges too constrained by register classes.

Fixes <rdar://problem/10466609>

llvm-svn: 145899
 2011-12-06 02:06:50 +00:00
Lang Hames
a7f56028f8 Kill off the LoopSplitter. It's not being used or maintained. 
llvm-svn: 145897
 2011-12-06 01:57:59 +00:00
Bill Wendling
e7c74617e5 Add a comment. 
llvm-svn: 145896
 2011-12-06 01:57:48 +00:00
Jim Grosbach
4aba5ca564 Tidy up value checking. 
llvm-svn: 145895
 2011-12-06 01:53:17 +00:00
NAKAMURA Takumi
c626e04fa2 MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc. 
llvm-svn: 145894
 2011-12-06 01:48:32 +00:00
Lang Hames
29572733bb Update PBQP's analysis usage to reflect the requirements of the inline spiller. 
llvm-svn: 145893
 2011-12-06 01:45:57 +00:00
Chad Rosier
70dd1f98af [arm-fast-isel] Doublewords only require word-alignment. 
rdar://10528060

llvm-svn: 145891
 2011-12-06 01:44:17 +00:00
Jakob Stoklund Olesen
af85f53dd0 Align ARM constant pool islands via their basic block. 
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

llvm-svn: 145890
 2011-12-06 01:43:02 +00:00
Jakob Stoklund Olesen
e53ed273d9 Use logarithmic units for basic block alignment. 
This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.

CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.

Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.

Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.

llvm-svn: 145889
 2011-12-06 01:26:19 +00:00
Bill Wendling
6e3adcc60a The compact encoding of the registers are 3-bits each. Make sure we shift the 
value over that much.

llvm-svn: 145888
 2011-12-06 01:26:14 +00:00
Jim Grosbach
0fd3f58ea2 Fix ARM handling of tBcc branch relaxation. 
rdar://10069056

llvm-svn: 145885
 2011-12-06 01:08:19 +00:00
Jakob Stoklund Olesen
e60dea48ec Use an existing function. 
llvm-svn: 145883
 2011-12-06 00:51:12 +00:00
Jim Grosbach
633ce3426c Move target-specific logic out of generic MCAssembler. 
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.

llvm-svn: 145881
 2011-12-06 00:47:03 +00:00
Nick Lewycky
d59dcc5ddb Expose a switch for the new gcov format. 
llvm-svn: 145880
 2011-12-06 00:29:13 +00:00
Chad Rosier
7096fea51c Probably not a good idea to convert a single vector load into a memcpy. We 
don't do this now, but add a test case to prevent this from happening in the
future.
Additional test for rdar://9892684

llvm-svn: 145879
 2011-12-06 00:19:08 +00:00
Jim Grosbach
c3c8c0eddd Tidy up. Hard tabs. 
llvm-svn: 145878
 2011-12-06 00:13:09 +00:00
Jim Grosbach
93874e36fa Switch MCAssembler to method names starting w/ lower-case. 
per http://llvm.org/docs/CodingStandards.html#ll_naming

llvm-svn: 145873
 2011-12-06 00:03:48 +00:00
Jim Grosbach
fe71651f99 Simple branch relaxation for Thumb2 Bcc instructions. 
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.

llvm-svn: 145871
 2011-12-05 23:45:46 +00:00
Nick Lewycky
389fa6c38d Silence tsan false-positives (tsan can't track things which are only safe due to 
memory fences) in statistics registration, which works the same way that
ManagedStatic registration does.

llvm-svn: 145869
 2011-12-05 23:07:05 +00:00
Chad Rosier
4f8c6f6a9c Update comment. 
llvm-svn: 145866
 2011-12-05 22:53:09 +00:00
Chad Rosier
c50cbc5a65 Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio 
where this would be bad as the backend shouldn't have a problem inlining small
memcpys.
rdar://10510150

llvm-svn: 145865
 2011-12-05 22:37:00 +00:00
Jim Grosbach
74bbb6454e Tweak ADDrr fix. Bad check for explicit .w 
llvm-svn: 145863
 2011-12-05 22:27:04 +00:00
Jim Grosbach
898ab7e4ec Thumb2 prefer ADD register encoding T2 to T3 when possible. 
rdar://10529664

llvm-svn: 145860
 2011-12-05 22:16:39 +00:00
Akira Hatanaka
bdefd49aa5 Add definitions of 64-bit extract and insert instrucions and make 
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.

llvm-svn: 145853
 2011-12-05 21:26:34 +00:00
Akira Hatanaka
ba16541b01 Split ExtIns into two base classes and have instructions EXT and INS derive from 
them.

llvm-svn: 145852
 2011-12-05 21:14:28 +00:00
Jim Grosbach
655b017748 Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348

llvm-svn: 145851
 2011-12-05 21:06:26 +00:00
Akira Hatanaka
b119dd5891 Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and 
O32 with relocation-model=pic too.

llvm-svn: 145850
 2011-12-05 21:03:03 +00:00
Jim Grosbach
9c017fb254 ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.

llvm-svn: 145846
 2011-12-05 20:29:59 +00:00
Jim Grosbach
8a902ce8de Fix previous commit. Oops. 
llvm-svn: 145844
 2011-12-05 20:12:26 +00:00
Jim Grosbach
8681f76f38 Tidy up. No functional change. 
llvm-svn: 145843
 2011-12-05 20:09:44 +00:00
Jim Grosbach
7b62c2f71d ARM assmebler parsing for two-operand VMUL instructions. 
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.

rdar://10522016

llvm-svn: 145842
 2011-12-05 19:55:46 +00:00
Hal Finkel
8b1e460cd9 enable PPC register scavenging by default (update tests and remove some FIXMEs) 
llvm-svn: 145819
 2011-12-05 17:55:17 +00:00
Hal Finkel
1a4a59ed2a don't include CR bit subregs in callee-saved list 
llvm-svn: 145818
 2011-12-05 17:55:12 +00:00
Hal Finkel
67924a349b add register pressure for CR regs 
llvm-svn: 145816
 2011-12-05 17:54:17 +00:00
Benjamin Kramer
f274d5feac Add a little heuristic to Value::isUsedInBasicBlock to speed it up for small basic blocks. 
- Calling getUser in a loop is much more expensive than iterating over a few instructions.
- Use it instead of the open-coded loop in AddrModeMatcher.
- 5% speedup on ARMDisassembler.cpp Release builds.

llvm-svn: 145810
 2011-12-05 17:23:27 +00:00
Craig Topper
e873d61004 Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions. 
llvm-svn: 145804
 2011-12-05 07:27:14 +00:00
Craig Topper
02e1c33dca Clean up and optimizations to the X86 shuffle lowering code. No functional change. 
llvm-svn: 145803
 2011-12-05 06:56:46 +00:00
Nadav Rotem
1a91e4381d Add support for vectors of pointers. 
llvm-svn: 145801
 2011-12-05 06:29:09 +00:00
Eric Christopher
5697266013 Add inline subprogram names to the name lookup table since they may 
not get there any other way.

llvm-svn: 145789
 2011-12-04 06:02:38 +00:00
Bob Wilson
f054e82281 Fix 80-column issues. 
llvm-svn: 145783
 2011-12-04 00:52:23 +00:00
Anton Korobeynikov
e2277de6a7 Emit the ctors in the proper order on ARM/EABI. 
Maybe some targets should use this as well.

Patch by Evgeniy Stepanov!

llvm-svn: 145781
 2011-12-03 23:49:37 +00:00
Venkatraman Govindaraju
a942dee2b8 Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since 
AnalyzeBranch doesn't change the successor, just the order.

llvm-svn: 145779
 2011-12-03 21:24:48 +00:00
Benjamin Kramer
ab489e4c97 Simplify code. No functionality change. 
-3% on ARMDissasembler.cpp.

llvm-svn: 145773
 2011-12-03 16:18:22 +00:00
Benjamin Kramer
4ff0db784c Clear the new cache. 
llvm-svn: 145771
 2011-12-03 15:19:55 +00:00
Benjamin Kramer
ed1cd704e0 Add a "seen blocks" cache to LVI to avoid a linear scan over the whole cache just to remove no blocks from the maps. 
-15% on ARMDisassembler.cpp (Release build).  It's not that great to add another
layer of caching to the caching-heavy LVI but I don't see a better way.

llvm-svn: 145770
 2011-12-03 15:16:45 +00:00
Sanjoy Das
fe35e107cd Check for stack space more intelligently. 
libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit.  This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit.  This should result in lesser calls to __morestack.

llvm-svn: 145766
 2011-12-03 09:32:07 +00:00
Sanjoy Das
d1c3d82afe Fix a bug in the x86-32 code generated for segmented stacks. 
Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp.  This isn't correct since __morestack expects the call
to be followed directly by a ret.

This commit also adjusts the relevant test-case.

llvm-svn: 145765
 2011-12-03 09:21:07 +00:00
Nick Lewycky
2b2f028dcc Creating multiple JITs on X86 in multiple threads causes multiple writes (of 
the same value) to this variable. This code could be refactored, but it doesn't
matter since the old JIT is going away. Add tsan annotations to ignore the
race.

llvm-svn: 145745
 2011-12-03 02:45:50 +00:00
Chad Rosier
d1968c9ed6 [arm-fast-isel] Unaligned stores of floats require special care. 
rdar://10510150

llvm-svn: 145742
 2011-12-03 02:21:57 +00:00
Pete Cooper
32e376f7e1 Fixed deadstoreelimination bug where negative indices were incorrectly causing the optimisation to occur 
Turns out long long + unsigned long long is unsigned.  Doh!

Fixes http://llvm.org/bugs/show_bug.cgi?id=11455

llvm-svn: 145731
 2011-12-03 00:04:30 +00:00
Chad Rosier
d830d783e2 Add support for constant folding the pow intrinsic. 
rdar://10514247

llvm-svn: 145730
 2011-12-03 00:00:03 +00:00
Jim Grosbach
fb734dff3c ARM NEON VEXT aliases for data type suffices. 
llvm-svn: 145726
 2011-12-02 23:34:39 +00:00
Jim Grosbach
b15f862d86 ARM VEXT tighten up operand classes a bit. 
llvm-svn: 145722
 2011-12-02 22:57:57 +00:00
Jim Grosbach
3b245f9c39 ARM VST1 single lane assembly parsing. 
llvm-svn: 145718
 2011-12-02 22:34:51 +00:00
Nick Lewycky
7d0d3c2d58 Move global variables in TargetMachine into new TargetOptions class. As an API 
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714
 2011-12-02 22:16:29 +00:00
Jim Grosbach
82ae7f46ea ARM VLD1 single lane assembly parsing. 
llvm-svn: 145712
 2011-12-02 22:01:52 +00:00
Jim Grosbach
cbde5d4877 ARM encoder method needs the physical register number, not the enum. 
llvm-svn: 145711
 2011-12-02 22:01:25 +00:00
Chad Rosier
b3b2871bbf [arm-fast-isel] After promoting a function parameter be sure to update the 
argument value type.  Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467

llvm-svn: 145701
 2011-12-02 20:25:18 +00:00
Jim Grosbach
a568ef0db6 Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

llvm-svn: 145693
 2011-12-02 18:52:30 +00:00
Benjamin Kramer
c477861998 Fix quadratic behavior in InlineFunction by fetching the personality function of the callee once and not for every invoke in the caller. 
The callee is usually smaller than the caller, too. This reduces the compile
time of ARMDisassembler.cpp by 32% (Release build). It still takes ages to
compile though.

llvm-svn: 145690
 2011-12-02 18:37:31 +00:00
Jim Grosbach
129c6dbc32 Check for error after InstantiateMultclassDef. 
llvm-svn: 145689
 2011-12-02 18:33:03 +00:00
Jan Sjödin
81ee97461c Add XOP feature flag. 
llvm-svn: 145682
 2011-12-02 15:14:37 +00:00
Craig Topper
c67b7d7e2c Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions 
llvm-svn: 145681
 2011-12-02 08:18:41 +00:00
Craig Topper
d381116357 Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors. 
llvm-svn: 145680
 2011-12-02 07:16:01 +00:00
Hal Finkel
c90c9f608e remove unneeded FIXME comment 
llvm-svn: 145679
 2011-12-02 04:58:17 +00:00
Hal Finkel
9ffa9b3c7f make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instruction in Sequence is a Noop 
llvm-svn: 145677
 2011-12-02 04:58:07 +00:00
Hal Finkel
e0f1d3fc22 update PPC 940 hazard rec. to function in postRA mode 
llvm-svn: 145676
 2011-12-02 04:58:02 +00:00
Chad Rosier
fdca220a9e Fix a few more places where TargetData/TargetLibraryInfo is not being passed. 
Add FIXMEs to places that are non-trivial to fix.

llvm-svn: 145661
 2011-12-02 01:26:24 +00:00
Jim Grosbach
d5c0c63223 ARM start parsing VLD1 single lane instructions. 
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.

llvm-svn: 145655
 2011-12-02 00:35:16 +00:00
Chad Rosier
a1a79d5df4 Abuse of mass replace isn't warranted even when the build is failing. Thanks 
for the suggestion, Eric.

llvm-svn: 145643
 2011-12-01 23:16:03 +00:00
Chad Rosier
c9879f3554 Fix build by not assuming TLI is guaranteed. Will have to track down cases where 
TLI isn't being passed to ensure we don't miss opportunities to fold calls.

llvm-svn: 145641
 2011-12-01 22:38:31 +00:00
Chad Rosier
4d25975a28 Prevent library calls from being folded if -fno-builtin has been specified. 
rdar://10500969

llvm-svn: 145639
 2011-12-01 22:14:50 +00:00
Dylan Noblesmith
9678a90d8f CodeGen: fix CMake build 
Missing file from r145629.

llvm-svn: 145634
 2011-12-01 21:49:23 +00:00
Dylan Noblesmith
ab2a910083 ExecutionEngine: honor optimization level 
It was getting ignored after r144788.

Also fix an accidental implicit cast from the OptLevel enum
to an optional bool argument. MSVC warned on this, but gcc
didn't.

llvm-svn: 145633
 2011-12-01 21:49:21 +00:00
Chad Rosier
0b4bd4832a Last bit of TargetLibraryInfo propagation. Also fixed a case for TargetData 
where it appeared beneficial to pass.
More of rdar://10500969

llvm-svn: 145630
 2011-12-01 21:29:16 +00:00
Anshuman Dasgupta
f754c8bf8e Add a deterministic finite automaton based packetizer for VLIW architectures 
llvm-svn: 145629
 2011-12-01 21:10:21 +00:00
David Blaikie
a787220c76 Fix unreachable return & simplify some branches. 
llvm-svn: 145627
 2011-12-01 20:58:30 +00:00
Sanjoy Das
5cc5730434 Dummy commit to check commit access. 
llvm-svn: 145619
 2011-12-01 19:15:08 +00:00
Pete Cooper
c708e83499 Improved fix for abs(val) != 0 to check other similar case. Also fixed style issues and confusing comment 
llvm-svn: 145618
 2011-12-01 19:13:26 +00:00
Kostya Serebryany
78bd9e81b4 [asan] two minor fixes: use UnreachableInst after the neverreturn function call; use report_fatal_error when blacklist file can not be found 
llvm-svn: 145611
 2011-12-01 18:54:53 +00:00
Chad Rosier
aafbda2d54 Add missing functions. 
llvm-svn: 145608
 2011-12-01 18:26:19 +00:00
Benjamin Kramer
95a0674b1b Autodetect bulldozers. 
llvm-svn: 145607
 2011-12-01 18:24:17 +00:00
Chad Rosier
7610c57a02 Add a few more functions to TargetLibraryInfo. More of rdar://10500969. 
llvm-svn: 145596
 2011-12-01 17:54:37 +00:00
Eric Christopher
4aa8024569 For 64-bit the rest of the general regs are ok for the q constraint. Make 
sure we can emit both the high and low versions of those registers.

Fixes rdar://10392864

llvm-svn: 145579
 2011-12-01 08:12:41 +00:00
David Blaikie
d951c64db1 Add some missing anchors. 
llvm-svn: 145578
 2011-12-01 08:00:17 +00:00
Eli Friedman
ad916965a6 Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>. 
llvm-svn: 145573
 2011-12-01 04:49:21 +00:00
Pete Cooper
7e03b7250d Added instcombine pattern to spot comparing -val or val against 0. 
(val != 0) == (-val != 0) so "abs(val) != 0" becomes "val != 0"

Fixes <rdar://problem/10482509>

llvm-svn: 145563
 2011-12-01 03:58:40 +00:00
Chad Rosier
49a66381f7 Propagate TargetLibraryInfo throughout ConstantFolding.cpp and 
InstructionSimplify.cpp.  Other fixups as needed.
Part of rdar://10500969

llvm-svn: 145559
 2011-12-01 03:08:23 +00:00
Nick Lewycky
4047e7c476 Make use of "getScalarType()". No functionality change. 
llvm-svn: 145556
 2011-12-01 02:39:36 +00:00
Eli Friedman
85c0054183 Small fix for assembler generation on Darwin PPC64. Patch by Michael Kostylev. PR11437. 
llvm-svn: 145553
 2011-12-01 01:43:47 +00:00
Kostya Serebryany
aa616ec887 make asan work at -O0, llvm part. Patch by glider@google.com 
llvm-svn: 145530
 2011-11-30 22:19:26 +00:00
Jan Sjödin
2dfb343ffa Support for encoding all FMA4 instructions and tablegen patterns for all 
remaining FMA4 instructions and intrinsics with tests.

llvm-svn: 145525
 2011-11-30 22:09:42 +00:00
Eli Friedman
2d9e4aa665 Make GlobalMerge honor the preferred alignment on globals without an explicitly specified alignment. 
<rdar://problem/10497732>.

llvm-svn: 145523
 2011-11-30 21:54:15 +00:00
Matt Beaumont-Gay
07afe588d4 Remove unused variable 
llvm-svn: 145517
 2011-11-30 19:53:11 +00:00
Jim Grosbach
6b2f6389cc ARM parsing for VLD1 all lanes, with writeback. 
llvm-svn: 145510
 2011-11-30 19:35:44 +00:00
Chad Rosier
8c6d695c1e Add a few functions to TargetLibraryInfo. 
llvm-svn: 145508
 2011-11-30 19:19:00 +00:00
Jim Grosbach
fa9f6ccd62 ARM parsing for VLD1 two register all lanes, no writeback. 
llvm-svn: 145504
 2011-11-30 18:21:25 +00:00
Benjamin Kramer
fbdf17c667 X86: Turns out bulldozer also supports sse42 and lzcnt. 
While at it remove the barcelona/instanbul/shanghai subtargets, they're
unsupported by GCC and look pretty broken.

llvm-svn: 145494
 2011-11-30 15:48:16 +00:00
Benjamin Kramer
359fde3539 X86: Add subtargets for AMD's bulldozer. 
llvm-svn: 145493
 2011-11-30 15:27:46 +00:00
Nadav Rotem
f8e096f4ee X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479). 
llvm-svn: 145488
 2011-11-30 10:13:37 +00:00
Craig Topper
2a0fc05456 Add instruction selection support for AVX2 horizontal add/sub instructions. 
llvm-svn: 145487
 2011-11-30 09:10:50 +00:00
Craig Topper
0ac9bb8aa1 Merge VPERM2F128/VPERM2I128 ISD node types. 
llvm-svn: 145485
 2011-11-30 07:47:51 +00:00
Craig Topper
43b885cff4 Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128. 
llvm-svn: 145483
 2011-11-30 06:25:25 +00:00
Andrew Trick
247f749767 LSR: handle the expansion of phi operands that use postinc forms of the IV. 
Fixes PR11431: SCEVExpander::expandAddRecExprLiterally(const llvm::SCEVAddRecExpr*): Assertion `(!isa<Instruction>(Result) || SE.DT->dominates(cast<Instruction>(Result), Builder.GetInsertPoint())) && "postinc expansion does not dominate use"' failed.

llvm-svn: 145482
 2011-11-30 06:07:54 +00:00
Chad Rosier
8f94cb4dd5 Whitespace. 
llvm-svn: 145470
 2011-11-30 01:59:59 +00:00
Chad Rosier
8b15aca551 Alphabetize TargetLibraryInfo enum and fix doxygen comments. No functional 
change intended.

llvm-svn: 145468
 2011-11-30 01:51:49 +00:00
Jim Grosbach
693ce8291c ARM parsing aliases for VLD1 single register all lanes. 
llvm-svn: 145464
 2011-11-30 01:09:44 +00:00
Chad Rosier
c5fa9f413a Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable 
(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is 
specified.
rdar://10466410

llvm-svn: 145460
 2011-11-29 23:57:10 +00:00
Jim Grosbach
9adabf4dde Tidy up a bit. 
llvm-svn: 145458
 2011-11-29 23:51:09 +00:00
Jim Grosbach
ccc984051d Add comment. 
llvm-svn: 145456
 2011-11-29 23:33:40 +00:00
Jim Grosbach
29147b45a5 ARM parsing aliases for data-size suffices on VST1. 
llvm-svn: 145454
 2011-11-29 23:21:31 +00:00
Akira Hatanaka
fd548b69f5 Change names for MIPS "generic" processors defined in Mips.td to match what GNU 
tools use. Patch by Simon Atanasyan.

"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"

llvm-svn: 145451
 2011-11-29 23:08:41 +00:00
Jim Grosbach
538759efa7 ARM assembly parsing and encoding for four-register VST1. 
llvm-svn: 145450
 2011-11-29 22:58:48 +00:00
Evan Cheng
5c1efd630b Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins. 
llvm-svn: 145448
 2011-11-29 22:48:34 +00:00
Jim Grosbach
5418e87582 ARM assembly parsing and encoding for three-register VST1. 
llvm-svn: 145442
 2011-11-29 22:38:04 +00:00
Jakob Stoklund Olesen
5d6a4584d9 Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions. 
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

llvm-svn: 145440
 2011-11-29 22:27:25 +00:00
Stepan Dyatkovskiy
56753569db Potential bug in RewriteLoopBodyWithConditionConstant: use iterator should not be changed inside the uses enumeration loop. 
llvm-svn: 145432
 2011-11-29 20:34:39 +00:00
Chad Rosier
0ff2f46d12 If fast-isel fails, remove dead instructions generated during the failed 
attempt.  

llvm-svn: 145425
 2011-11-29 19:40:47 +00:00
Andrew Trick
a6c63bda2e comment. 
llvm-svn: 145422
 2011-11-29 19:33:49 +00:00
Daniel Dunbar
4e00f5f8fd build/CMake: Finish removal of add_llvm_library_dependencies. 
llvm-svn: 145420
 2011-11-29 19:25:30 +00:00
Duncan Sands
97cc6da56c Fix a theoretical problem (not seen in the wild): if different instances of a 
weak variable are compiled by different compilers, such as GCC and LLVM, while
LLVM may increase the alignment to the preferred alignment there is no reason to
think that GCC will use anything more than the ABI alignment.  Since it is the
GCC version that might end up in the final program (as the linkage is weak), it
is wrong to increase the alignment of loads from the global up to the preferred
alignment as the alignment might only be the ABI alignment.

Increasing alignment up to the ABI alignment might be OK, but I'm not totally
convinced that it is.  It seems better to just leave the alignment of weak
globals alone.

llvm-svn: 145413
 2011-11-29 18:26:38 +00:00
Michael J. Spencer
5fade79478 MC/X86/COFF: Allow quotes in names when targeting MS/Windows, 
as MC is the only assembler we support.

This splits MS/Windows and GNU/Windows ASM infos into two seperate classes.
While there is currently only one difference, full MS C++ ABI support will
require many more.

llvm-svn: 145409
 2011-11-29 18:00:06 +00:00
Danil Malyshev
5ce4e1a9d3 Fixed ObjectFile functions: 
- getSymbolOffset() renamed as getSymbolFileOffset()
- getSymbolFileOffset(), getSymbolAddress(), getRelocationAddress() returns same result for ELFObjectFile, MachOObjectFile and COFFObjectFile.
- added getRelocationOffset()
- fixed MachOObjectFile::getSymbolSize()
- fixed MachOObjectFile::getSymbolSection()
- fixed MachOObjectFile::getSymbolOffset() for symbols without section data.

llvm-svn: 145408
 2011-11-29 17:40:10 +00:00
Elena Demikhovsky
735cff1fa8 Fixed vsqrt.ss intrinsic usage - order of input operands was wrong. 
Added a test.
Thanks Bruno for reviewing the patch.

llvm-svn: 145403
 2011-11-29 15:00:45 +00:00
Craig Topper
637e60afdd Fix shuffle decoding for memory forms for (V)SHUFPS/D. 
llvm-svn: 145392
 2011-11-29 07:58:09 +00:00
Craig Topper
4550fc2649 Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD. 
llvm-svn: 145390
 2011-11-29 07:49:05 +00:00
NAKAMURA Takumi
b92661d00a [Win32] Catch exceptions (eg. segfault) on waiting for invoked clang from the driver. 
clang/lib/Driver/Driver.cpp: Don't pass through negative exit status, or parent would be confused.

llvm::sys::Program::Wait(): Suppose 0x8000XXXX and 0xC000XXXX as abnormal exit code and pass it as negative value.

Win32 Exception Handler: Exit with ExceptionCode on an unhandle exception.

llvm-svn: 145389
 2011-11-29 07:47:04 +00:00
Craig Topper
aca91b9f14 Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled. 
llvm-svn: 145376
 2011-11-29 05:37:58 +00:00
Craig Topper
a6c1d25798 Correctly mark VPERM2F128 as being an FP instruction and add execution domain fixing support to convert it to VPERM2I128 for AVX2. 
llvm-svn: 145370
 2011-11-29 03:57:34 +00:00
Bill Wendling
d26e0c541c MachO doesn't support the protected visibility. Don't default to 'global' here. <rdar://problem/10396775> 
llvm-svn: 145368
 2011-11-29 02:39:58 +00:00
Andrew Trick
63f81b112e SCEV fix. In general, Add/Mul expressions should not inherit NSW/NUW. 
This reverts r139450, fixes r139453, and adds much needed comments and a
unit test.

llvm-svn: 145367
 2011-11-29 02:16:38 +00:00
Andrew Trick
975fe6c09b Make SCEV print <nsw><nuw> for Add/MulExpr. 
llvm-svn: 145364
 2011-11-29 02:06:35 +00:00
Bill Wendling
0f9a3f91ae On MachO, the pointer to the personality function should always be in the 
non_lazy_symbol_pointers section (__IMPORT,__pointers). Ignore the 'hidden' part
since that will place it in the wrong section.
<rdar://problem/10443720>

llvm-svn: 145356
 2011-11-29 01:43:20 +00:00
Eli Friedman
1d55ba306b Zap some completely ridiculous code. There's probably a miscompile here, but I don't really want to try to write a testcase involving an invoke returning a pointer to a varargs function... 
llvm-svn: 145347
 2011-11-29 01:18:23 +00:00
Jim Grosbach
168778090c Better fix for ARM MOVT relocation encoding of thumb bit. 
Replaces r145318 with a more targetted fix for the relocation handling.

llvm-svn: 145346
 2011-11-29 01:15:25 +00:00
Daniel Dunbar
93f8ddd97a build: Update CMakeLists.txt. 
llvm-svn: 145341
 2011-11-29 00:33:14 +00:00
Daniel Dunbar
7c4510b4de edis: Sink EDMain.cpp into lib/MC/MCDisassembler. 
- This fixes some layering violations and matches how we handle the llvm-c lib,
   for example.

llvm-svn: 145338
 2011-11-29 00:25:57 +00:00
Jim Grosbach
ea721eb4b3 Thumb2 only force the fixup thumb bit for data relocations. 
rdar://10493453

llvm-svn: 145318
 2011-11-28 23:39:00 +00:00
Eli Friedman
bc47555417 Add a missing safety check to ProcessUGT_ADDCST_ADD. Fixes PR11438. 
llvm-svn: 145316
 2011-11-28 23:32:19 +00:00
Jim Grosbach
d6fb8be618 Remove obsolete FIXME. 
llvm-svn: 145313
 2011-11-28 23:23:58 +00:00
Eli Friedman
473a76a0df Make SelectionDAG::InferPtrAlignment use llvm::ComputeMaskedBits instead of duplicating the logic for globals. Make llvm::ComputeMaskedBits handle GlobalVariables slightly more aggressively, to match what InferPtrAlignment knew how to do. 
llvm-svn: 145304
 2011-11-28 22:48:22 +00:00