1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 19:42:54 +02:00
Commit Graph

45 Commits

Author SHA1 Message Date
Vasileios Kalintiris
dd324fafb5 Revert "[mips] Promote the result of SETCC nodes to GPR width."
This reverts commit r262316.

It seems that my change breaks an out-of-tree chromium buildbot, so
I'm reverting this in order to investigate the situation further.

llvm-svn: 262387
2016-03-01 20:25:43 +00:00
Vasileios Kalintiris
e8b2910afd [mips] Promote the result of SETCC nodes to GPR width.
Summary:
This patch modifies the existing comparison, branch, conditional-move
and select patterns, and adds new ones where needed. Also, the updated
SLT{u,i,iu} set of instructions generate a GPR width result.

The majority of the code changes in the Mips back-end fix the wrong
assumption that the result of SETCC nodes always produce an i32 value.
The changes in the common code path account for the fact that in 64-bit
MIPS targets, i1 is promoted to i32 instead of i64.

Reviewers: dsanders

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D10970

llvm-svn: 262316
2016-03-01 10:08:01 +00:00
Toma Tabacu
e49117b828 [mips] Add the SoftFloat MipsSubtarget feature.
Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled.

Reviewers: dsanders, echristo

Reviewed By: dsanders

Subscribers: jfb, llvm-commits, mpf

Differential Revision: http://reviews.llvm.org/D9053

llvm-svn: 236713
2015-05-07 10:29:52 +00:00
Vasileios Kalintiris
fe5bb204f0 [mips] Enable code generation for MIPS-III.
Summary:
This commit enables the MIPS-III target and adds support for code
generation of SELECT nodes. We have to use pseudo-instructions with
custom inserters for these nodes as MIPS-III CPUs do not have
conditional-move instructions.

Depends on D6212

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6464

llvm-svn: 224128
2014-12-12 15:16:46 +00:00
Vasileios Kalintiris
40712e048d [mips] Support SELECT nodes for targets that don't have conditional-move instructions.
Summary:
For Mips targets that do not have conditional-move instructions, ie. targets
before MIPS32 and MIPS-IV, we have to insert a diamond control-flow
pattern in order to support SELECT nodes. In order to do that, we add
pseudo-instructions with a custom inserter that emits the necessary
control-flow that selects the correct value.

With this patch we add complete support for code generation of Mips-II targets
based on the LLVM test-suite.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6212

llvm-svn: 224124
2014-12-12 14:41:37 +00:00
Daniel Sanders
c3777d6de2 [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6
Summary:
c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to
dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's
(like the GPR comparisons).

mov[fntz] have been replaced by seleqz and selnez. These instructions
conditionally zero a register based on a bool in a GPR. The results can
then be or'd together to act as a select without, for example, requiring a third
register read port.

mov[fntz].[ds] have been replaced with sel.[ds]

MIPS64r6 currently generates unnecessary sign-extensions for most selects.
This is because the result of a SETCC is currently an i32. Bits 32-63 are
undefined in i32 and the behaviour of seleqz/selnez would otherwise depend
on undefined bits. Later, we will fix this by making the result of SETCC an
i64 on MIPS64 targets.

Depends on D3958

Reviewers: jkolek, vmedic, zoran.jovanovic

Reviewed By: vmedic, zoran.jovanovic

Differential Revision: http://reviews.llvm.org/D4003

llvm-svn: 210777
2014-06-12 13:39:06 +00:00
Daniel Sanders
5cba0c9900 [mips] Marked up instructions added in MIPS-IV and tested that IAS for -mcpu=mips[123] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-IV that was available in MIPS32

A small number of instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now.

Depends on D3676

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3677

llvm-svn: 208414
2014-05-09 14:06:17 +00:00
Daniel Sanders
1cc95dd8b6 [mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of FGRPredicates/GPRPredicates
Summary:
No functional change (confirmed by diffing tablegen-erated files).

Depends on D3642

Reviewers: vmedic, dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3645

llvm-svn: 208213
2014-05-07 14:25:43 +00:00
Daniel Sanders
9bda911eb9 [mips] Continue splitting Instruction.Predicates into smaller lists and re-join them with !listconcat
Summary:
Move IsGP64bit into GPRPredicates, and IsFP64bit/NotFP64bit into FGRPredicates

No functional change (confirmed by diffing tablegen-erated files).

Depends on D3639

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3640

llvm-svn: 208201
2014-05-07 12:48:37 +00:00
Daniel Sanders
078f32bcd8 [mips] Split Instruction.Predicates into smaller lists and re-join them with !listconcat
Summary:
The overall idea is to chop the Predicates list into subsets that are
usually overridden independently. This allows subclasses to partially
override the predicates of their superclasses without having to re-add all
the existing predicates.

This patch starts the process by moving HasStdEnc into a new
EncodingPredicates list and almost everything else into
AdditionalPredicates.

It has revealed a couple likely bugs where 'let Predicates' has removed
the HasStdEnc predicate.

No functional change (confirmed by diffing tablegen-erated files).

Depends on D3549, D3506

Reviewers: vmedic

Differential Revision: http://reviews.llvm.org/D3550

llvm-svn: 208184
2014-05-07 10:27:09 +00:00
Daniel Sanders
dc36787564 [mips] Move HasStdEnc to the front of the predicates lists.
Summary:
This will make it easier to prove that a more complicated change in the
following commit is non-functional.

No functional change.

Depends on D3506

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3549

llvm-svn: 208179
2014-05-07 09:58:05 +00:00
Daniel Sanders
25e96ccaa5 [mips] Remove two more redundant 'let Predicates = [HasStdEnc]' statements that were missed
Summary:
The InstSE class already initializes Predicates to [HasStdEnc].

No functional change (confirmed by diffing tablegen-erated files before and
after)

Differential Revision: http://reviews.llvm.org/D3548

llvm-svn: 207558
2014-04-29 17:04:30 +00:00
Daniel Sanders
b3f0be8f2e [mips] Fix more incorrect uses of HasMips64 and isMips64()
Summary:
- Conditional moves acting on 64-bit GPR's should require MIPS-IV rather than MIPS64
- ISD::MUL, and ISD::MULH[US] should be lowered on all 64-bit ISA's

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

I've added additional testcases to cover as much of the codegen changes
affecting MIPS-IV as I can. Where I've been unable to find an existing
MIPS64 testcase that can be re-used for MIPS-IV (mainly tests covering
ISD::GlobalAddress and similar), I at least agree that MIPS-IV should
behave like MIPS64. Further testcases that are fixed by this patch will follow
in my next commit. The testcases from that commit that fail for MIPS-IV without
this patch are:
    LLVM :: CodeGen/Mips/2010-07-20-Switch.ll
    LLVM :: CodeGen/Mips/cmov.ll
    LLVM :: CodeGen/Mips/eh-dwarf-cfa.ll
    LLVM :: CodeGen/Mips/largeimmprinting.ll
    LLVM :: CodeGen/Mips/longbranch.ll
    LLVM :: CodeGen/Mips/mips64-f128.ll
    LLVM :: CodeGen/Mips/mips64directive.ll
    LLVM :: CodeGen/Mips/mips64ext.ll
    LLVM :: CodeGen/Mips/mips64fpldst.ll
    LLVM :: CodeGen/Mips/mips64intldst.ll
    LLVM :: CodeGen/Mips/mips64load-store-left-right.ll
    LLVM :: CodeGen/Mips/sint-fp-store_pattern.ll

Reviewers: dsanders

Reviewed By: dsanders

CC: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3343

llvm-svn: 206183
2014-04-14 15:44:42 +00:00
Daniel Sanders
4d85938877 [mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD]
No functional change since the InstrItinData's have been duplicated.

llvm-svn: 199727
2014-01-21 11:28:03 +00:00
Daniel Sanders
b055d0c245 [mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
  II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
  II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
  II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
  II_SR[AL]V, II_SUBU, II_XOR

No functional change since the InstrItinData's have been duplicated.

This is necessary because the classes are shared between all schedulers.

Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.

llvm-svn: 199391
2014-01-16 14:27:20 +00:00
Zoran Jovanovic
427d20b793 Support for microMIPS FPU instructions 2.
llvm-svn: 198009
2013-12-25 10:09:27 +00:00
Akira Hatanaka
b84769b3d7 [mips] Set instruction itineraries of loads, stores and conditional moves.
llvm-svn: 190219
2013-09-06 23:28:24 +00:00
Vladimir Medic
a00506588f This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
llvm-svn: 190148
2013-09-06 12:41:17 +00:00
Akira Hatanaka
5d76bb1499 [mips] Fix instruction definitions that were incorrectly marked as code-gen-only.
llvm-svn: 188690
2013-08-19 19:08:03 +00:00
Akira Hatanaka
c05b5c3dae [mips] Rename accumulator register classes and FP register operands.
llvm-svn: 188020
2013-08-08 21:54:26 +00:00
Akira Hatanaka
1290d365ec [mips] Rename register classes CPURegs and CPU64Regs.
llvm-svn: 187832
2013-08-06 23:08:38 +00:00
Akira Hatanaka
4c91ec2ed9 [mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of
instructions defined in MipsInstrInfo.td as codegen-only instructions.

llvm-svn: 187828
2013-08-06 23:01:10 +00:00
Akira Hatanaka
d0c19bc118 [mips] Define instruction itineraries IIArith and IILogic.
No functionality change.

llvm-svn: 187468
2013-07-31 00:55:34 +00:00
Vladimir Medic
aafcb477fd This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
llvm-svn: 187410
2013-07-30 10:12:14 +00:00
Akira Hatanaka
689acaf88f [mips] Fix FP conditional move instructions to have explicit FP condition code
register operands.

llvm-svn: 187242
2013-07-26 20:51:20 +00:00
Akira Hatanaka
e6ef926882 [mips] Fix floating point branch, comparison, and conditional move instructions
to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.

No intended functionality change.

llvm-svn: 187233
2013-07-26 19:01:56 +00:00
Vladimir Medic
e3aeddca47 This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient.
llvm-svn: 186397
2013-07-16 10:07:14 +00:00
Akira Hatanaka
d2f7ed089c [mips] Fix inefficient code generation.
This patch eliminates the need to emit a constant move instruction when this
pattern is matched:

(select (setgt a, Constant), T, F)

The pattern above effectively turns into this:

(conditional-move (setlt a, Constant + 1), F, T)

llvm-svn: 176384
2013-03-01 21:52:08 +00:00
Akira Hatanaka
a064b57260 Fix indentation.
llvm-svn: 176380
2013-03-01 21:22:21 +00:00
Akira Hatanaka
014ed59039 [mips] Refactor conditional move instructions.
llvm-svn: 171511
2013-01-04 19:16:38 +00:00
Akira Hatanaka
9b0bb584d7 [mips] Delete all floating point instruction classes that are no longer used.
No functionality change.

llvm-svn: 170084
2012-12-13 02:05:02 +00:00
Akira Hatanaka
8a20e0e5f7 [mips] Modify definitions of floating point conditional move instructions.
No functionality change.

llvm-svn: 170080
2012-12-13 01:41:15 +00:00
Akira Hatanaka
57161323ed [mips] Shorten predicate name.
llvm-svn: 169579
2012-12-07 03:06:09 +00:00
Akira Hatanaka
9894b24617 [mips] Remove unnecessary predicates.
llvm-svn: 169577
2012-12-07 03:01:24 +00:00
Akira Hatanaka
d1b2b96ed5 1. introduce MipsPat in place of Pat in order to exclude those from
being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered

Patch by Reed Kotler.

llvm-svn: 158470
2012-06-14 21:03:23 +00:00
Akira Hatanaka
2a600ff5f4 This patch adds a predicate to existing mips32 and mips64 so that those
instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234
2012-05-22 03:10:09 +00:00
Akira Hatanaka
574e68feec Add another peephole pattern for conditional moves.
llvm-svn: 156460
2012-05-09 02:29:29 +00:00
Akira Hatanaka
ecb1cd1ce4 Add disassembler to MIPS.
Patch by Vladimir Medic. 

llvm-svn: 154935
2012-04-17 18:03:21 +00:00
Akira Hatanaka
cecb440c11 Revert r153924. There were buildbot failures.
llvm-svn: 153925
2012-04-03 02:51:09 +00:00
Akira Hatanaka
058b0cfb55 MIPS disassembler support.
Patch by Vladimir Medic.

llvm-svn: 153924
2012-04-03 02:20:58 +00:00
Jia Liu
bdcd314be3 remove blanks, and some code format
llvm-svn: 151625
2012-02-28 07:46:26 +00:00
Jia Liu
ecc08b8cfe add Emacs tag and fix some comment error in file headers
llvm-svn: 150775
2012-02-17 01:23:50 +00:00
Bruno Cardoso Lopes
edc2e30d42 Final patch that completes old JIT support for Mips:
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378
2011-10-18 17:50:36 +00:00
Akira Hatanaka
4939842b5a Add definitions of conditional moves with 64-bit operands. Comment out code for
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 

llvm-svn: 142226
2011-10-17 18:53:29 +00:00
Akira Hatanaka
e8cb50da87 Move class and instruction definitions for conditional moves to a seperate file.
llvm-svn: 142220
2011-10-17 18:43:19 +00:00