RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 19:42:54 +02:00
Code Issues Projects Releases Wiki Activity
77,317 Commits 4 Branches 5 Tags 704 MiB
e76ba1b654
Commit Graph

5450 Commits

Author SHA1 Message Date
Chad Rosier
e76ba1b654 A branch predicated on a constant can just FastEmit an unconditional branch. 
llvm-svn: 143086
 2011-10-27 00:21:16 +00:00
Chad Rosier
e3141f4f8b Add a TODO comment. FastISel works by parsing each basic block from the bottom 
up.  Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle.  This creates many more 
opportunities for target specific fast-isel.

llvm-svn: 143079
 2011-10-26 23:34:37 +00:00
Chad Rosier
75378507e3 Factor a little more code into EmitCmp, which should have been done in the first 
place.  No functional change intended.

llvm-svn: 143078
 2011-10-26 23:25:44 +00:00
Chad Rosier
52109646da Use EmitCmp in SelectBranch. No functional change intended. 
llvm-svn: 143076
 2011-10-26 23:17:28 +00:00
Chad Rosier
3f38cb48de Factor out an EmitCmp function that can be used by both SelectCmp and 
SelectBranch.  No functional change intended.

llvm-svn: 143072
 2011-10-26 22:47:55 +00:00
Jim Grosbach
e3c6fa663f Thumb2 ldr pc-relative encoding fixes. 
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.

More of rdar://10348687

llvm-svn: 143068
 2011-10-26 22:22:01 +00:00
Jim Grosbach
4597f361f6 ARM parse parenthesized expressions for label references. 
Partial fix for rdar://10348687.

llvm-svn: 143063
 2011-10-26 21:14:08 +00:00
Lang Hames
d87e366c7f Make sure short memsets on ARM lower to stores, even when optimizing for size. 
llvm-svn: 143055
 2011-10-26 20:56:52 +00:00
Jim Grosbach
5a61a956cb Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern. 
llvm-svn: 143034
 2011-10-26 17:28:15 +00:00
James Molloy
9afc8b08f7 Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance. 
llvm-svn: 143023
 2011-10-26 08:53:19 +00:00
Bill Wendling
b0dc0e18ca Use a worklist to prevent the iterator from becoming invalidated because of the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot. 
llvm-svn: 143018
 2011-10-26 07:16:18 +00:00
Evan Cheng
941d5c148f Revert part of r142530. The patch potentially hurts performance especially 
on Darwin platforms where -Os means optimize for size without hurting
performance.

llvm-svn: 143002
 2011-10-26 01:17:44 +00:00
Jim Grosbach
fabe0f2f0b ARM assembly parsing and encoding for VLD1 with writeback. 
Four entry register lists.

llvm-svn: 142882
 2011-10-25 00:14:01 +00:00
Jim Grosbach
e8a2edd71c Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction. 
llvm-svn: 142877
 2011-10-24 23:40:46 +00:00
Jim Grosbach
688186941f ARM assembly parsing and encoding for VLD1 w/ writeback. 
Three entry register list variation.

llvm-svn: 142876
 2011-10-24 23:26:05 +00:00
Eli Friedman
652497e03c Don't crash on variable insertelement on ARM. PR10258. 
llvm-svn: 142871
 2011-10-24 23:08:52 +00:00
Evan Cheng
b792a7d95b ARMConstantPoolMBB::print should print BB number. 
llvm-svn: 142867
 2011-10-24 23:01:03 +00:00
Jim Grosbach
cf4fba1dd0 ARM assembly parsing and encoding for VLD1 w/ writeback. 
One and two length register list variants.

llvm-svn: 142861
 2011-10-24 22:16:58 +00:00
Jim Grosbach
4a6508dd4e ARM refactor am6offset usage for VLD1. 
Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.

llvm-svn: 142853
 2011-10-24 21:45:13 +00:00
Owen Anderson
b0e09258e7 Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. 
llvm-svn: 142817
 2011-10-24 18:04:29 +00:00
Dan Gohman
898ed35860 Change this overloaded use of Sched::Latency to be an overloaded 
use of Sched::ILP instead, as Sched::Latency is going away.

llvm-svn: 142813
 2011-10-24 17:55:11 +00:00
Jim Grosbach
eceea163ef Thumb2 LDM instructions can target PC. Make sure to encode it. 
PR11220

llvm-svn: 142801
 2011-10-24 17:16:24 +00:00
Benjamin Kramer
03065133c3 Move various generated tables into read-only memory, fixing up const correctness along the way. 
llvm-svn: 142726
 2011-10-22 16:50:00 +00:00
Bill Wendling
66327a8d0e The different flavors of ARM have different valid subsets of registers. Check 
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2

llvm-svn: 142706
 2011-10-22 00:29:28 +00:00
Jim Grosbach
d964cf8939 Assembly parsing for 4-register sequential variant of VLD2. 
llvm-svn: 142704
 2011-10-21 23:58:57 +00:00
Jim Grosbach
a6e536367e Assembly parsing for 2-register sequential variant of VLD2. 
llvm-svn: 142691
 2011-10-21 22:21:10 +00:00
Jim Grosbach
68dfc88f95 Assembly parsing for 4-register variant of VLD1. 
llvm-svn: 142682
 2011-10-21 20:35:01 +00:00
Jim Grosbach
2c1ca90ac9 Assembly parsing for 3-register variant of VLD1. 
llvm-svn: 142675
 2011-10-21 20:02:19 +00:00
Jim Grosbach
6bb38d0e97 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
 2011-10-21 18:54:25 +00:00
Owen Anderson
ccc76e17cc Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing. 
llvm-svn: 142669
 2011-10-21 18:43:28 +00:00
Jim Grosbach
9b539fab9d Nuke an #if0 that got accidentally left in. 
llvm-svn: 142658
 2011-10-21 16:59:08 +00:00
Jim Grosbach
a1d54f2c7a whitespace. 
llvm-svn: 142657
 2011-10-21 16:56:40 +00:00
Jim Grosbach
501c72cdc5 Remove some outdated comments. 
llvm-svn: 142653
 2011-10-21 16:14:12 +00:00
Owen Anderson
2021ad2133 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. 
llvm-svn: 142626
 2011-10-20 22:23:58 +00:00
Owen Anderson
24f04143bc Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures. 
llvm-svn: 142618
 2011-10-20 21:24:38 +00:00
Bill Wendling
3e34fd8604 Add missing operand. <rdar://problem/10313323> 
llvm-svn: 142615
 2011-10-20 20:37:11 +00:00
Jim Grosbach
547dde4517 Tidy up. Trailing whitespace. 
llvm-svn: 142591
 2011-10-20 17:28:20 +00:00
Jim Grosbach
e9d1df8266 ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. 
llvm-svn: 142583
 2011-10-20 15:04:25 +00:00
Jim Grosbach
972f26d936 ARM VTBX (one register) assembly parsing and encoding. 
llvm-svn: 142581
 2011-10-20 14:48:50 +00:00
Chad Rosier
38661ab3ce Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :( 
llvm-svn: 142557
 2011-10-20 00:07:12 +00:00
James Molloy
73a2a8a45e Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size. 
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.

The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.

Fixes PR11087.

llvm-svn: 142530
 2011-10-19 14:11:07 +00:00
Bill Wendling
aebac9fc6c Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool. 
llvm-svn: 142485
 2011-10-19 09:24:02 +00:00
Bill Wendling
0da8817ea2 Remove some dead code. 
llvm-svn: 142484
 2011-10-19 09:04:11 +00:00
Bill Wendling
bc96b4c75a Emit the MOVT instruction only if the # LPads is > 64K. 
llvm-svn: 142460
 2011-10-18 23:19:55 +00:00
Bill Wendling
72d4e0a695 For Thumb mode, we need to use a constant pool if the value is too large to be 
used with the CMP instruction.

llvm-svn: 142458
 2011-10-18 23:11:05 +00:00
Jim Grosbach
6a932d6ad1 ARM VTBL (one register) assembly parsing and encoding. 
llvm-svn: 142441
 2011-10-18 23:02:30 +00:00
Bill Wendling
da2d6a83c8 Use the integer compare when the value is small enough. Use the "move into a 
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.

llvm-svn: 142440
 2011-10-18 22:52:20 +00:00
Bill Wendling
f200722cbc Use the integer compare when the value is small enough. Use the "move into a 
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.

llvm-svn: 142437
 2011-10-18 22:49:07 +00:00
Bill Wendling
6900914506 The value we're comparing against may be too large for the ARM CMP 
instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>

llvm-svn: 142431
 2011-10-18 22:11:18 +00:00
Bill Wendling
198609713e The immediate may be too large for the CMP instruction. Move it into a register 
and use that in the CMP.
<rdar://problem/10305266>

llvm-svn: 142429
 2011-10-18 21:55:58 +00:00