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Commit Graph

95 Commits

Author SHA1 Message Date
Christopher Lamb
1a102eecb0 Allow ComplexExpressions in InstrInfo.td files to be slightly more... complex! ComplexExpressions can now have attributes which affect how TableGen interprets
the pattern when generating matchin code. 

The first (and currently, only) attribute causes the immediate parent node of the ComplexPattern operand to be passed into the matching code rather than the node at the root of the entire DAG containing the pattern.

llvm-svn: 46606
2008-01-31 07:27:46 +00:00
Dan Gohman
13d1327796 Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.

llvm-svn: 46538
2008-01-30 00:15:11 +00:00
Chris Lattner
41717f6989 This commit changes:
1. Legalize now always promotes truncstore of i1 to i8. 
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
   X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
   safe.

The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:

_foo:
	fldt	20(%esp)
	fldt	4(%esp)
	faddp	%st(1)
	movl	36(%esp), %eax
	fstps	(%eax)
	ret

instead of:

_foo:
	subl	$4, %esp
	fldt	24(%esp)
	fldt	8(%esp)
	faddp	%st(1)
	fstps	(%esp)
	movl	40(%esp), %eax
	movss	(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$4, %esp
	ret

llvm-svn: 46140
2008-01-17 19:59:44 +00:00
Chris Lattner
6846e346a8 rename SDTRet -> SDTNone.
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017
2008-01-15 22:02:54 +00:00
Chris Lattner
dee5700386 add SDNPSideEffect node property declaration
llvm-svn: 45825
2008-01-10 05:48:23 +00:00
Chris Lattner
3aa2fc1b5c add SDNPMayLoad to the 'load' sdnode definition. This is enough to get all the x86
instructions (with patterns) that load memory marked, for example.

llvm-svn: 45818
2008-01-10 04:44:32 +00:00
Chris Lattner
5489888580 rename isStore -> mayStore to more accurately reflect what it captures.
llvm-svn: 45656
2008-01-06 08:36:04 +00:00
Chris Lattner
8b4b75c771 Change the 'isStore' inferrer to look for 'SDNPMayStore'
instead of "ISD::STORE".  This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores).  This allows us to remove
more explicit isStore flags from the .td files.

Finally, add a warning for when a .td file contains an explicit 
isStore and tblgen is able to infer it.

llvm-svn: 45654
2008-01-06 06:44:58 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Chris Lattner
8a1dfeecab add a immAllZerosV_bc pattern fragment for consistency with others.
llvm-svn: 44303
2007-11-24 19:02:07 +00:00
Bill Wendling
934fcd87e7 Unifacalize the CALLSEQ{START,END} stuff.
llvm-svn: 44045
2007-11-13 09:19:02 +00:00
Evan Cheng
0a3651a70d Rename keyword "modify" -> "implicit".
llvm-svn: 42282
2007-09-25 01:48:59 +00:00
Evan Cheng
bd4b11cfa9 Initial support for multi-result patterns:
1.
[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 (modify EFLAGS)]
This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS.
2.
def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()>
Similar to #1 except this is used for def : Pat patterns.

llvm-svn: 41897
2007-09-12 23:30:14 +00:00
Dale Johannesen
a85f11d870 Long double patch 4 of N: initial x87 implementation.
Lots of problems yet but some simple things work.

llvm-svn: 40847
2007-08-05 18:49:15 +00:00
Christopher Lamb
73c3cd47cc Add selection DAG nodes for subreg insert/extract. PR1350
llvm-svn: 40516
2007-07-26 07:34:40 +00:00
Dan Gohman
0ba554c0c8 Fix comments about vectors to use the current wording.
llvm-svn: 39921
2007-07-16 14:29:03 +00:00
Lauro Ramos Venancio
bc32d90b46 Implement "general dynamic", "initial exec" and "local exec" TLS models for
X86 32 bits.

llvm-svn: 36283
2007-04-20 21:38:10 +00:00
Jim Laskey
23ed7d2625 Make LABEL a builtin opcode.
llvm-svn: 33537
2007-01-26 14:34:52 +00:00
Chris Lattner
6c55120e31 Fix predicates for unindexed stores so they don't accidentally match indexed
stores.

llvm-svn: 31735
2006-11-14 19:13:39 +00:00
Evan Cheng
22bb3ba200 Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
llvm-svn: 31596
2006-11-09 18:44:21 +00:00
Evan Cheng
019b921f3b Added indexed store node and patfrag's.
llvm-svn: 31576
2006-11-08 23:02:11 +00:00
Evan Cheng
9048e1010b Change load PatFrag to ignore indexed load.
llvm-svn: 31210
2006-10-26 21:55:50 +00:00
Evan Cheng
fe5bb5dbe6 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
Evan Cheng
ca66f49574 Add properties to ComplexPattern.
llvm-svn: 30891
2006-10-11 21:03:53 +00:00
Evan Cheng
9b31a4d4ed Naming consistency.
llvm-svn: 30878
2006-10-11 07:10:22 +00:00
Evan Cheng
d22f3dd3ed Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
Evan Cheng
494e8e6971 Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.

llvm-svn: 30714
2006-10-04 00:56:09 +00:00
Evan Cheng
cc433bd065 Vector extract / insert index operand should have ptr type.
llvm-svn: 28798
2006-06-15 08:19:05 +00:00
Nate Begeman
7ed816f900 JumpTable support! What this represents is working asm and jit support for
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
2006-04-22 18:53:45 +00:00
Evan Cheng
5e80563052 Renamed AddedCost to AddedComplexity.
llvm-svn: 27843
2006-04-19 20:38:28 +00:00
Evan Cheng
318120f8ad Allow "let AddedCost = n in" to increase pattern complexity.
llvm-svn: 27834
2006-04-19 18:07:24 +00:00
Chris Lattner
254683a3df Add a new vnot_conv predicate for matching vnot's where the allones vector is
bitconverted from some other type.

llvm-svn: 27724
2006-04-15 23:39:14 +00:00
Evan Cheng
5da48f30bb Add vector_extract and vector_insert nodes.
llvm-svn: 27303
2006-03-31 19:21:16 +00:00
Chris Lattner
d5da541d42 Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
llvm-svn: 27201
2006-03-28 00:40:33 +00:00
Evan Cheng
2a36326bb0 Changed isBuildVectorAllOnesInteger to isBuildVectorAllOnes.
llvm-svn: 27166
2006-03-27 06:59:32 +00:00
Evan Cheng
5809827989 Add immAllZerosV helper
llvm-svn: 27148
2006-03-26 09:51:39 +00:00
Chris Lattner
f83db1efe6 add a vnot helper node for matching 'not' on vectors
llvm-svn: 27132
2006-03-25 23:00:08 +00:00
Chris Lattner
b0e8c6dd7f Add new intrinsic node definitions for tblgen use
llvm-svn: 27100
2006-03-25 02:29:35 +00:00
Chris Lattner
b979b51e39 Shuffle some includes around
llvm-svn: 27073
2006-03-24 18:52:35 +00:00
Chris Lattner
8e14f3544b expose intrinsic info to the targets.
llvm-svn: 27070
2006-03-24 18:44:11 +00:00
Evan Cheng
a4db61ddc1 x86 ISD::SCALAR_TO_VECTOR support.
llvm-svn: 26911
2006-03-21 00:33:35 +00:00
Chris Lattner
09ede9ec9f Add a build_vector node
llvm-svn: 26895
2006-03-20 06:18:01 +00:00
Chris Lattner
5892479894 add vector_shuffle
llvm-svn: 26891
2006-03-20 05:40:45 +00:00
Chris Lattner
4fd1599ab1 add support for the bitconvert node
llvm-svn: 26789
2006-03-16 01:29:53 +00:00
Andrew Lenharth
2d36f9d389 relax fcopysign
llvm-svn: 26649
2006-03-09 17:47:22 +00:00
Andrew Lenharth
78af2795b3 fcopysign support
llvm-svn: 26640
2006-03-09 14:57:36 +00:00
Chris Lattner
999aa36a04 remove the read/write port/io intrinsics.
llvm-svn: 26479
2006-03-03 00:19:58 +00:00
Nate Begeman
9c0ab71f4a kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255
2006-02-17 05:43:56 +00:00
Nate Begeman
224405b002 Whoops, didn't mean to check this in yet.
llvm-svn: 26250
2006-02-17 00:56:19 +00:00
Nate Begeman
7269afbf38 Add a missing and useful pat frag
llvm-svn: 26249
2006-02-17 00:51:06 +00:00