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10113 Commits

Author SHA1 Message Date
Daniel Dunbar
e6ee7409b9 Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang. 
Conflicts:

	lib/CodeGen/MachineSink.cpp

llvm-svn: 106614
 2010-06-23 00:48:25 +00:00
Stuart Hastings
bf77774e2f Less incorrect handling of zero-length bitfields. Radars 7992077 and 8093043. 
llvm-svn: 106611
 2010-06-23 00:31:14 +00:00
Bruno Cardoso Lopes
db9027d95d Add AVX compare packed instructions 
llvm-svn: 106600
 2010-06-22 23:37:59 +00:00
Dan Gohman
c33529255a Loosen up this test so that it doesn't depend as much on register 
allocation details.

llvm-svn: 106599
 2010-06-22 23:32:47 +00:00
Dan Gohman
2ac2a33a1b Fix OptimizeMax to handle an odd case where one of the max operands 
is another max which folds. This fixes PR7454.

llvm-svn: 106594
 2010-06-22 23:07:13 +00:00
Bruno Cardoso Lopes
424b206ad4 Reapply support for AVX unpack and interleave instructions, with 
testcases this time.

llvm-svn: 106593
 2010-06-22 23:02:38 +00:00
Bruno Cardoso Lopes
93ec8dcd01 Add AVX MOV{SS,SD}{rr,rm} instructions 
llvm-svn: 106588
 2010-06-22 22:38:56 +00:00
Bob Wilson
cb414cca8d Thumb1 functions using @llvm.returnaddress were not saving the incoming LR. 
Radar 8031193.

llvm-svn: 106582
 2010-06-22 22:04:24 +00:00
Eric Christopher
48c062d65b Move a 64-bit test to the 64-bit file. Fixes an llvm-mc assertion 
during test runs.

llvm-svn: 106577
 2010-06-22 21:11:51 +00:00
Dale Johannesen
dd9d7b11da Add SSE so these actually pass on non-X86 hosts. 
llvm-svn: 106575
 2010-06-22 20:54:03 +00:00
Bruno Cardoso Lopes
a176972a1b Fix a subtle multiclass bug: when using class inheritance on 
a toplevel 'defm', make sure to properly resolve references.

llvm-svn: 106570
 2010-06-22 20:30:50 +00:00
Bill Wendling
1e7edfa27a Corresponding test changes for r106564. 
llvm-svn: 106569
 2010-06-22 20:30:14 +00:00
Mon P Wang
c0fb410ae3 Move v-binop-widen tests to X86 since they don't work on all platforms 
llvm-svn: 106562
 2010-06-22 19:40:50 +00:00
Jakob Stoklund Olesen
ddb09c5258 Remove the SimpleJoin optimization from SimpleRegisterCoalescing. 
Measurements show that it does not speed up coalescing, so there is no reason
the keep the added complexity around.

Also clean out some unused methods and static functions.

llvm-svn: 106548
 2010-06-22 16:13:57 +00:00
Dan Gohman
a3bc6b13f7 Allow "exhaustive" trip count evaluation on phi nodes with all 
constant operands.

llvm-svn: 106537
 2010-06-22 13:15:46 +00:00
Evan Cheng
a1ebf91a39 Tail merging pass shall not break up IT blocks. rdar://8115404 
llvm-svn: 106517
 2010-06-22 01:18:16 +00:00
Dan Gohman
bcc040be1b Teach two-address lowering how to unfold a load to open up commuting 
opportunities. For example, this lets it emit this:

   movq (%rax), %rcx
   addq %rdx, %rcx

instead of this:

   movq %rdx, %rcx
   addq (%rax), %rcx

in the case where %rdx has subsequent uses. It's the same number
of instructions, and usually the same encoding size on x86, but
it appears faster, and in general, it may allow better scheduling
for the load.

llvm-svn: 106493
 2010-06-21 22:17:20 +00:00
Evan Cheng
167a8655c7 Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed. 
llvm-svn: 106481
 2010-06-21 21:21:14 +00:00
Dan Gohman
cbede71023 Make this test more robust in case LLVM ever decides to align the global 
variable differently.

llvm-svn: 106454
 2010-06-21 19:56:27 +00:00
Dale Johannesen
baf342fdab Add missing FileCheck call. 
llvm-svn: 106443
 2010-06-21 18:46:08 +00:00
Devang Patel
79e2417a08 test case for r106438. 
llvm-svn: 106439
 2010-06-21 18:37:23 +00:00
Dale Johannesen
ef3db5dea3 Fix PR 7433. Silly typo in non-Darwin ARM tail call 
handling, plus correct R9 handling in that mode.

llvm-svn: 106434
 2010-06-21 18:21:49 +00:00
Eric Christopher
8909d46ea2 Add some codegen patterns for x86_64-linux-gnu tls codegen matching. 
Based on a patch by Patrick Marlier!

llvm-svn: 106433
 2010-06-21 18:21:27 +00:00
Kalle Raiskila
5e3c80d1f8 Add the check to the testcase of r106419. 
llvm-svn: 106421
 2010-06-21 15:11:51 +00:00
Kalle Raiskila
2001fd19b9 Mark the SPU 'lr' instruction to never have side effects. 
This allows the fast regiser allocator to remove redundant 
register moves.
Update a set of tests that depend on the register allocator
to be linear scan. 

llvm-svn: 106420
 2010-06-21 15:08:16 +00:00
Kalle Raiskila
cbd0b7c43b Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats. 
llvm-svn: 106419
 2010-06-21 14:42:19 +00:00
Kalle Raiskila
a30e45e2d3 Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithm 
used to choke llc with the attached test.
 

llvm-svn: 106411
 2010-06-21 10:17:36 +00:00
Evan Cheng
c18fbafa74 Fix a crash caused by dereference of MBB.end(). rdar://8110842 
llvm-svn: 106399
 2010-06-20 00:54:38 +00:00
Dan Gohman
fcb0f1936b Include the use kind along with the expression in the key of the 
use sharing map. The reconcileNewOffset logic already forces a
separate use if the kinds differ, so incorporating the kind in the
key means we can track more sharing opportunities.

More sharing means fewer total uses to track, which means smaller
problem sizes, which means the conservative throttles don't kick
in as often.

llvm-svn: 106396
 2010-06-19 21:29:59 +00:00
Dan Gohman
cec5b682b6 Fix ScalarEvolution's "exhaustive" trip count evaluation code to avoid 
assuming that loops are in canonical form, as ScalarEvolution doesn't
depend on LoopSimplify itself. Also, with indirectbr not all loops can
be simplified. This fixes PR7416.

llvm-svn: 106389
 2010-06-19 14:17:24 +00:00
Bruno Cardoso Lopes
c41dfa7cad Refactor aliased packed logical instructions, also add 
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.

llvm-svn: 106374
 2010-06-19 02:44:01 +00:00
Evan Cheng
f40b8f0e32 Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them. 
llvm-svn: 106368
 2010-06-19 01:01:32 +00:00
Bruno Cardoso Lopes
d6d12f37c6 Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions 
llvm-svn: 106366
 2010-06-19 00:37:31 +00:00
Chris Lattner
ed5a217085 fix rdar://7873482 by teaching the instruction encoder to emit 
segment prefixes.  Daniel wrote most of this patch.

llvm-svn: 106364
 2010-06-19 00:34:00 +00:00
Evan Cheng
e9ba3241a3 Move ARM if-conversion before post-ra scheduling. 
llvm-svn: 106355
 2010-06-18 23:32:07 +00:00
Evan Cheng
b5fadc47e0 Allow ARM if-converter to be run after post allocation scheduling. 
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.

llvm-svn: 106344
 2010-06-18 23:09:54 +00:00
Jakob Stoklund Olesen
3f0825f966 TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREG 
instructions, but it doesn't really understand live ranges, so the first
INSERT_SUBREG uses an implicitly defined register.

Fix it in LiveVariableAnalysis by adding the <undef> flag.

llvm-svn: 106333
 2010-06-18 22:29:44 +00:00
Evan Cheng
aa0ff1ae01 Fix an inverted condition. 
llvm-svn: 106330
 2010-06-18 22:17:13 +00:00
Jakob Stoklund Olesen
a1d49fabaf When using ADDri to get the address of a stack object, 255 is a conservative 
limit on the offset that can be materialized without using the register
scavenger.

llvm-svn: 106312
 2010-06-18 20:59:25 +00:00
Dan Gohman
b5ec637e57 Revert r106304 (105548 and friends), which are the SCEVComplexityCompare 
optimizations. There is still some nondeterminism remaining.

llvm-svn: 106306
 2010-06-18 19:54:20 +00:00
Bruno Cardoso Lopes
71ad64af39 Teach tablegen how to inherit from classes in 'defm' definitions. 
The rule is simple: only inherit from a class list if they come
in the end, after the last multiclass.

llvm-svn: 106305
 2010-06-18 19:53:41 +00:00
Dan Gohman
527b570925 Reapply 105540, 105542, and 105548, and revert r105732. 
llvm-svn: 106304
 2010-06-18 19:26:04 +00:00
Dale Johannesen
a441c8fd45 Enable tail calls on ARM by default, with some 
basic tests.

This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
  B.W  <label in other function>
which it has not seen before, at least from llvm-based
compilers.  I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.

llvm-svn: 106299
 2010-06-18 19:00:18 +00:00
Jakob Stoklund Olesen
6c387d99ca Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86 
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.

llvm-svn: 106289
 2010-06-18 16:49:33 +00:00
Dan Gohman
6c3d683d19 Don't write a file named "&1". 
llvm-svn: 106269
 2010-06-18 01:49:17 +00:00
Dan Gohman
e375e96f0d Disable indvars on loops when LoopSimplify form is not available. 
This fixes PR7333.

llvm-svn: 106267
 2010-06-18 01:35:11 +00:00
Dan Gohman
9d7cf23808 Don't maintain a set of deleted nodes; instead, use a HandleSDNode 
to track a node over CSE events. This fixes PR7368.

llvm-svn: 106266
 2010-06-18 01:24:29 +00:00
Bruno Cardoso Lopes
ea44492375 Add {mix,max}{ss,sd}{rr,rm} AVX forms. 
llvm-svn: 106264
 2010-06-18 01:12:56 +00:00
Dan Gohman
8185674354 Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass, 
which is faster, simpler, and less surprising.

llvm-svn: 106263
 2010-06-18 01:05:21 +00:00
Dan Gohman
08da31dc83 Make this test less fragile. 
llvm-svn: 106255
 2010-06-18 00:06:03 +00:00