1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 03:23:01 +02:00
Commit Graph

140492 Commits

Author SHA1 Message Date
Simon Pilgrim
f01009c55d [SelectionDAG] Add support for splatted vectors in SUB opcode
llvm-svn: 286509
2016-11-10 21:57:42 +00:00
Simon Pilgrim
1cff91326f [X86] Add knownbits vector SUB test
llvm-svn: 286508
2016-11-10 21:50:23 +00:00
Matthias Braun
7ae7138a52 RegisterCoalescer: Ignore interferences for constant physregs
When copying to/from a constant register interferences can be ignored.

Also update the documentation for isConstantPhysReg() to make it more
obvious that this transformation is valid.

Differential Revision: https://reviews.llvm.org/D26106

llvm-svn: 286503
2016-11-10 21:22:47 +00:00
Yaxun Liu
a4fdadbaa3 AMDGPU: Emit runtime metadata as a note element in .note section
Currently runtime metadata is emitted as an ELF section with name .AMDGPU.runtime_metadata.

However there is a standard way to convey vendor specific information about how to run an ELF binary, which is called vendor-specific note element (http://www.netbsd.org/docs/kernel/elf-notes.html).

This patch lets AMDGPU backend emits runtime metadata as a note element in .note section.

Differential Revision: https://reviews.llvm.org/D25781

llvm-svn: 286502
2016-11-10 21:18:49 +00:00
Zachary Turner
739dd10ba5 Fix type ambiguity with std::max
llvm-svn: 286498
2016-11-10 20:35:21 +00:00
Zachary Turner
6d1aa9fbeb Fix initialization order error.
llvm-svn: 286497
2016-11-10 20:23:32 +00:00
Zachary Turner
cd93c0e109 [Support] Improve flexibility of binary blob formatter.
This makes it possible to indent a binary blob by a certain
number of bytes, and also makes some things more idiomatic.
Finally, it integrates this binary blob formatter into ScopedPrinter
which used to have its own implementation of this algorithm.

Differential Revision: https://reviews.llvm.org/D26477

llvm-svn: 286495
2016-11-10 20:16:45 +00:00
Zachary Turner
44dcd81f11 [PDB] Begin adding documentation for the PDB file format.
Differential Revision: https://reviews.llvm.org/D26374

llvm-svn: 286491
2016-11-10 19:24:21 +00:00
Adam Nemet
217f9f4002 [opt-viewer] Avoid duplicated remarks
This can happen if a pass is run multiple times or if the code is in a
header file which is included multiple times.

llvm-svn: 286489
2016-11-10 18:42:56 +00:00
Davide Italiano
5f48d9a859 [Target] Rename X86/ARM Assembly printer to reflect reality.
This shows up a lot profiling LTO testcases with -time-passes, so
better have a non confusing name.

llvm-svn: 286488
2016-11-10 18:39:31 +00:00
Eugene Zelenko
7aa413a524 Fix some Clang-tidy modernize-use-default and readability-redundant-member-init and Include What You Use warnings; other minor fixes.
Differential revision: https://reviews.llvm.org/D26087

llvm-svn: 286484
2016-11-10 18:02:34 +00:00
Nico Weber
443375fd3a Revert r286437 r286438, they caused PR30976
llvm-svn: 286483
2016-11-10 17:55:41 +00:00
Adam Nemet
f8a50d283f [OptDiag] Remove non-printable chars from function name
The r283656 did this in the remark arguments.  We also need to do this
in the main function attribute as that is written to YAML as well.

llvm-svn: 286482
2016-11-10 17:47:03 +00:00
Simon Pilgrim
9b52058816 [SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodes
llvm-svn: 286481
2016-11-10 17:43:52 +00:00
Dehao Chen
334f136dbd Add comments about why we put LoopSink pass at the very late stage.
llvm-svn: 286480
2016-11-10 17:42:18 +00:00
Simon Pilgrim
97b59349cb [X86] Add knownbits vector TRUNC test
In preparation for demandedelts support

llvm-svn: 286477
2016-11-10 17:24:33 +00:00
Teresa Johnson
db6785496f Restore part of "[ThinLTO] Prevent exporting of locals used/defined in module level asm"
This restores the part of r286297 that didn't require adding a
dependency from the Analysis to Object library. There are two parts
to the original fix, and this will address the handling for the case
where locals are used in module level asm.

The part that requires functionality in libObject handles local defs
in module level asm, and was reverted because our downstream build
of clang builds lib/Bitcode into a single library, and this new
dependency introduced a cycle there. I am trying to get that fixed
(see D26502), so for now that change isn't being restored

llvm-svn: 286475
2016-11-10 16:57:32 +00:00
Simon Pilgrim
789b18ba30 Use common SDLoc. NFCI.
llvm-svn: 286473
2016-11-10 16:47:09 +00:00
Simon Pilgrim
c228feab22 [SelectionDAG] Add support for vector demandedelts in MUL opcodes
llvm-svn: 286471
2016-11-10 16:27:42 +00:00
Asaf Badouh
d3240c52be reproducer for pr29002
https://reviews.llvm.org/D26449

llvm-svn: 286470
2016-11-10 16:27:27 +00:00
Tom Stellard
fca8e2011d AMDGPU: Add VI i16 support
Patch By: Wei Ding

Differential Revision: https://reviews.llvm.org/D18049

llvm-svn: 286464
2016-11-10 16:02:37 +00:00
Simon Pilgrim
d2824aa2f7 [X86] Add knownbits vector MUL test
In preparation for demandedelts support

llvm-svn: 286463
2016-11-10 15:57:33 +00:00
Simon Pilgrim
d9fcf3c063 [SelectionDAG] Add support for vector demandedelts in SRA opcodes
llvm-svn: 286461
2016-11-10 15:05:09 +00:00
Sanjay Patel
d261791644 [InstCombine] auto-generate better checks; NFC
Note that the existing metadata checking was re-added by hand because the 
script doesn't currently know how to generate checks for lines outside of 
functions.

llvm-svn: 286460
2016-11-10 14:58:17 +00:00
Simon Pilgrim
502e3f027d [X86] Add knownbits vector arithmetic shift test
In preparation for demandedelts support

llvm-svn: 286457
2016-11-10 14:46:24 +00:00
Simon Pilgrim
3091f96ce6 [DAGCombiner] Correctly extract the ConstOrConstSplat shift value for SHL nodes
We were failing to extract a constant splat shift value if the shifted value was being masked.

The (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV) combine was unnecessarily preventing this.

llvm-svn: 286454
2016-11-10 14:35:09 +00:00
Chad Rosier
1bd36b2600 Remove unnecessary check prefix directives. NFC.
llvm-svn: 286453
2016-11-10 14:28:44 +00:00
Simon Pilgrim
5a36ec9d38 [DAGCombiner] Show missed opportunity to UNDEF out-of-range SHL
Fails to match constant shift value due to presence of AND mask.

llvm-svn: 286452
2016-11-10 14:19:45 +00:00
Tobias Grosser
68e42a688d [RegionInfo] Add three tests that include infinite loops
These examples are variations that were inspired from a small subgraph taken
from paper.ll which are interesting as they show certain issues with infinite
loops.

llvm-svn: 286450
2016-11-10 13:56:19 +00:00
Simon Pilgrim
7f153a9a3d [SelectionDAG] Add support for vector demandedelts in SHL/SRL opcodes
llvm-svn: 286448
2016-11-10 13:52:42 +00:00
Simon Pilgrim
f00c22daa1 [X86] Add knownbits vector logical shift test
In preparation for demandedelts support

llvm-svn: 286447
2016-11-10 13:34:17 +00:00
Oliver Stannard
e6a1e88b9b [ARM] Thumb2 LDR (literal) should accept PC as the destination
The version of this instruction with the .w suffix already correctly accepts
this, but the alias without the .w did not.

Differential Revision: https://reviews.llvm.org/D26499

llvm-svn: 286446
2016-11-10 13:20:41 +00:00
Sanjoy Das
7a7b1db577 [SCEVExpander] Hoist unsigned divisons when safe
That is, when the divisor is a constant non-zero.

llvm-svn: 286438
2016-11-10 07:56:12 +00:00
Sanjoy Das
bc356bfa6b [SCEVExpander] Don't hoist divisions
Fixes PR30942.

llvm-svn: 286437
2016-11-10 07:56:09 +00:00
Sanjoy Das
b9e5e12feb Lift out a helper lambda; NFC
llvm-svn: 286436
2016-11-10 07:56:05 +00:00
Craig Topper
8969a9fe8d [AVX-512] Allow legacy cvtpd2dq intrinsics to select EVEX encoded instruction when available.
llvm-svn: 286435
2016-11-10 07:47:17 +00:00
Craig Topper
996de74ecd [AVX-512][X86] Convert avx_cvtt_ps2dq_256 and sse2_cvttps2dq intrinsics to ISD::FP_TO_SINT in the intrinsics table and delete patterns. While nearby also move CVTDQ2PS patterns into their instructions.
This allows these intrinsics to also use EVEX instructons.

llvm-svn: 286434
2016-11-10 07:24:52 +00:00
Craig Topper
6a3572c8b3 [X86] Convert int_x86_avx_cvtt_pd2dq_256 to fp_to_sint using the intrinsics table. Removes extra patterns and allows legacy intrinsic to select EVEX encoded instructions when available.
llvm-svn: 286433
2016-11-10 06:45:39 +00:00
Craig Topper
887fe1945d [X86] Move some custom patterns into the currently empty pattern of their corresponding instructions. NFC
llvm-svn: 286432
2016-11-10 06:45:37 +00:00
Craig Topper
2588e6440e [X86] Remove some patterns still referencing int_x86_sse2_cvttpd2dq that should have been removed in r286344. NFC
llvm-svn: 286431
2016-11-10 06:45:34 +00:00
Sanjoy Das
09edb6fc47 [SCEV] Eta reduce some lambdas; NFC
llvm-svn: 286429
2016-11-10 06:33:54 +00:00
Sanjoy Das
f79a7f58af [LangRef] Drop "experimental" caveat from operand bundles
I think we're past that point now.

llvm-svn: 286428
2016-11-10 06:21:10 +00:00
Craig Topper
3bc846bf9f [AVX-512] Add test cases to show missed opportunities for using VALIGND/Q to handle shuffles.
llvm-svn: 286425
2016-11-10 03:39:19 +00:00
Sanjay Patel
3a42ddfbd2 [InstCombine] avoid infinite loop from shuffle-extract-insert sequence (PR30923)
Removing the limitation in visitInsertElementInst() causes several regressions
because we're not prepared to fold sequences of shuffles or inserts and extracts
separated by shuffles. Fixing that appears to be a difficult mission because we
are purposely trying to avoid creating shuffles with arbitrary shuffle masks
because some targets may choke on those.

https://llvm.org/bugs/show_bug.cgi?id=30923

llvm-svn: 286423
2016-11-10 00:15:14 +00:00
Peter Collingbourne
53c709eaaf Re-apply r286384, "X86: Introduce the "relocImm" ComplexPattern, which represents a relocatable immediate.", with a fix for 32-bit x86.
Teach X86InstrInfo::analyzeCompare() not to crash on CMP and SUB instructions
that take a global address operand.

llvm-svn: 286420
2016-11-09 23:53:43 +00:00
Dylan McKay
391ac08575 [AVR] Add a selection of CodeGen tests
Summary: This adds all of the CodeGen tests which currently pass.

Reviewers: arsenm, kparzysz

Subscribers: japaric, wdng

Differential Revision: https://reviews.llvm.org/D26388

llvm-svn: 286418
2016-11-09 23:46:52 +00:00
Dylan McKay
6faa0c3ed4 [AVR] Add all of the machine code test suite
Summary: This adds all of the AVR machine code tests.

Reviewers: arsenm, kparzysz

Subscribers: wdng, japaric

Differential Revision: https://reviews.llvm.org/D26387

llvm-svn: 286417
2016-11-09 23:46:25 +00:00
Dehao Chen
a874afb484 Add isHotBB helper function to ProfileSummaryInfo
Summary: This will unify all BB hotness checks.

Reviewers: eraman, davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D26353

llvm-svn: 286415
2016-11-09 23:36:02 +00:00
Eli Friedman
4486441607 Preserve assumption cache in loop-rotate.
No testcase included because I can't figure out how to reduce it.
(It's easy to write a testcase where rotation clones an assume,
but that doesn't actually seem to trigger the crash in opt on
its own; maybe an issue with the laziness?)

Differential Revision: https://reviews.llvm.org/D26434

llvm-svn: 286410
2016-11-09 23:05:01 +00:00
Tim Northover
c0279a14c5 GlobalISel: fix typo. NFC
llvm-svn: 286408
2016-11-09 22:40:02 +00:00