1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-24 05:23:45 +02:00
Commit Graph

138051 Commits

Author SHA1 Message Date
Sanjay Patel
f29b6b5458 [x86] regenerate checks
llvm-svn: 281531
2016-09-14 20:21:28 +00:00
Sanjay Patel
8c715da81c [x86] regenerate checks
llvm-svn: 281529
2016-09-14 20:16:24 +00:00
Evgeniy Stepanov
8dd4aa2167 Revert "[ARM] Promote small global constants to constant pools"
Breaks Android tests by introducing text relocations to ARM binaries.

http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/25362/steps/run%20asan%20lit%20tests%20%5Barm%2Fbullhead-userdebug%2FMTC20F%5D/logs/stdio

llvm-svn: 281526
2016-09-14 20:02:30 +00:00
Sanjay Patel
bb5469d614 [x86] regenerate checks
llvm-svn: 281523
2016-09-14 19:42:03 +00:00
Davide Italiano
1946df91a4 [lib/LTO] Fix a typo. NFC.
llvm-svn: 281517
2016-09-14 18:48:43 +00:00
Matt Arsenault
6a290fc995 Revert "AMDGPU: Use SOPK compare instructions"
Accidentally committed

llvm-svn: 281514
2016-09-14 18:04:42 +00:00
Matt Arsenault
2196097c5a AMDGPU: Use SOPK compare instructions
llvm-svn: 281513
2016-09-14 18:03:53 +00:00
Adrian Prantl
f7b060540c Verifier: Mark orphaned DICompileUnits as a debug info failure.
This is a follow-up to r268778 that adds a couple of missing cases,
most notably orphaned compile units.

rdar://problem/28193346

llvm-svn: 281508
2016-09-14 17:30:37 +00:00
Matt Arsenault
186940fec6 Make analyzeBranch family of instruction names consistent
analyzeBranch was renamed to use lowercase first, rename
the related set to match.

llvm-svn: 281506
2016-09-14 17:24:15 +00:00
Matt Arsenault
3b94dad7d3 AArch64: Use TTI branch functions in branch relaxation
The main change is to return the code size from
InsertBranch/RemoveBranch.

Patch mostly by Tim Northover

llvm-svn: 281505
2016-09-14 17:23:48 +00:00
Sanjay Patel
d3ca66ea70 [x86] fix formatting; NFC
llvm-svn: 281504
2016-09-14 17:23:18 +00:00
Etienne Bergeron
446bf9baa1 [compiler-rt] Avoid instrumenting sanitizer functions
Summary:
Function __asan_default_options is called by __asan_init before the
shadow memory got initialized. Instrumenting that function may lead
to flaky execution.

As the __asan_default_options is provided by users, we cannot expect
them to add the appropriate function atttributes to avoid
instrumentation.

Reviewers: kcc, rnk

Subscribers: dberris, chrisha, llvm-commits

Differential Revision: https://reviews.llvm.org/D24566

llvm-svn: 281503
2016-09-14 17:18:37 +00:00
Simon Pilgrim
5f03f4e898 [X86][SSE] Improve recognition of i64 sitofp conversions that can be performed as i32 (PR29078)
Until AVX512DQ we only support i64/vXi64 sitofp conversion as scalars.

This patch sees if the sign bit extends far enough that we can truncate to a i32 type and then perform sitofp without loss of precision.

Differential Revision: https://reviews.llvm.org/D24345

llvm-svn: 281502
2016-09-14 17:15:26 +00:00
Chad Rosier
ceb19d1df2 [LoopInterchange] Typo. NFC.
llvm-svn: 281501
2016-09-14 17:12:30 +00:00
Chad Rosier
68d7bc3b4f [LoopInterchange] Add CL option to override cost threshold.
Mostly useful for getting consistent lit testing.

llvm-svn: 281500
2016-09-14 17:07:13 +00:00
Simon Pilgrim
43b58d8ddc [X86][SSE] Don't use PSHUFD directly - lower with generic shuffle
Remove the last user of the old getTargetShuffleNode helpers

llvm-svn: 281499
2016-09-14 17:04:22 +00:00
Sanjay Patel
d9f29ae5f3 getValueType().getScalarSizeInBits() -> getScalarValueSizeInBits(), round 2 ; NFCI
llvm-svn: 281498
2016-09-14 16:54:10 +00:00
Chad Rosier
77de429e07 [LoopInterchange] Cleanup debug whitespace. NFC.
llvm-svn: 281497
2016-09-14 16:43:19 +00:00
Sanjay Patel
bb652cfa0b getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCI
llvm-svn: 281495
2016-09-14 16:37:15 +00:00
Sanjay Patel
c514c5d741 getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCI
llvm-svn: 281493
2016-09-14 16:05:51 +00:00
Etienne Bergeron
2b47797a1e Fix typo in comment [NFC]
llvm-svn: 281492
2016-09-14 15:59:32 +00:00
Matt Arsenault
4086e0fffa AMDGPU: Support folding FrameIndex operands
This avoids test regressions in a future commit.

llvm-svn: 281491
2016-09-14 15:51:33 +00:00
Sanjay Patel
fe75137cbe getValueType().getScalarSizeInBits() -> getScalarValueSizeInBits() ; NFCI
llvm-svn: 281490
2016-09-14 15:43:44 +00:00
Sanjay Patel
5023a2bb82 getScalarType().getSizeInBits() -> getScalarSizeInBits() ; NFCI
llvm-svn: 281489
2016-09-14 15:21:00 +00:00
Matt Arsenault
9249507611 AMDGPU: Improve splitting 64-bit bit ops by constants
This addresses a TODO to handle operations besides and. This
also starts eliminating no-op operations with a constant that
can emerge later.

llvm-svn: 281488
2016-09-14 15:19:03 +00:00
Matthew Simpson
23308c98a2 [LV] Process pointer IVs with PHINodes in collectLoopUniforms
This patch moves the processing of pointer induction variables in
collectLoopUniforms from the consecutive pointer phase of the analysis to the
phi node phase. Previously, if a pointer induction variable was used by both a
scalarized non-memory instruction as well as a vectorized memory instruction,
we would incorrectly identify the pointer as uniform. Pointer induction
variables should be treated the same as other phi nodes. That is, they are
uniform if all users of the induction variable and induction variable update
are uniform.

Differential Revision: https://reviews.llvm.org/D24511

llvm-svn: 281485
2016-09-14 14:47:40 +00:00
James Molloy
30dc709e61 [ARM] Promote small global constants to constant pools
If a constant is unamed_addr and is only used within one function, we can save
on the code size and runtime cost of an indirection by changing the global's storage
to inside the constant pool. For example, instead of:

      ldr r0, .CPI0
      bl printf
      bx lr
    .CPI0: &format_string
    format_string: .asciz "hello, world!\n"

We can emit:

      adr r0, .CPI0
      bl printf
      bx lr
    .CPI0: .asciz "hello, world!\n"

This can cause significant code size savings when many small strings are used in one
function (4 bytes per string).

llvm-svn: 281484
2016-09-14 14:47:27 +00:00
Sjoerd Meijer
6b2a89b146 MCInstrDesc: this fixes an issue setting/getting member Flags, which
is an uint64_t. However, getter function getFlags returned an unsigned,
and in function hasProperty (1 << MCFlag) was used instead of (1ULL << MCFlag).

llvm-svn: 281483
2016-09-14 14:32:17 +00:00
Simon Pilgrim
55a7d3e6b5 [X86][SSE] Removed unused getTargetShuffleNode function
llvm-svn: 281481
2016-09-14 14:30:00 +00:00
Simon Pilgrim
a8f356133a [X86] Added i128 lshr+shl -> mask combine test
llvm-svn: 281480
2016-09-14 14:29:16 +00:00
Nemanja Ivanovic
05f2f7ea61 Fix code-gen crash on Power9 for insert_vector_elt with variable index (PR30189)
This patch corresponds to review:
https://reviews.llvm.org/D24021

In the initial implementation of this instruction, I forgot to account for
variable indices. This patch fixes PR30189 and should probably be merged into
3.9.1 (I'll open a bug according to the new instructions).

llvm-svn: 281479
2016-09-14 14:19:09 +00:00
Andrea Di Biagio
4c84c302a4 [InstCombine] Merged two test files and regenerated checks using update_test_checks.py. NFC.
llvm-svn: 281478
2016-09-14 14:18:21 +00:00
Silviu Baranga
193a6cf220 [StackProtector] Use INITIALIZE_TM_PASS instead of INITIALIZE_PASS
in order to make sure that its TargetMachine constructor is
registered.

This allows us to run the PEI machine pass with MIR input
(see PR30324).

llvm-svn: 281474
2016-09-14 14:09:43 +00:00
Nemanja Ivanovic
816d3f4f3f Adding missing directive for Power9.
There is currently no codegen for Power9 that depends on the directive
so this is NFC for now but will be important in the future. This was
missed in r268950 so I'm adding it now.

llvm-svn: 281473
2016-09-14 14:09:39 +00:00
Simon Pilgrim
a4ae5a2b5a [X86][SSE] Don't blend vector shifts with MOVSS/MOVSD directly, lower from generic shuffle
Shuffle lowering will correctly lower to MOVSS/MOVSD/PBLEND, improving commutation opportunities

llvm-svn: 281471
2016-09-14 14:08:18 +00:00
Kuba Brecka
603bab4445 [asan] Enable -asan-use-private-alias on Darwin/Mach-O, add test for ODR false positive with LTO (llvm part)
The '-asan-use-private-alias’ option (disabled by default) option is currently only enabled for Linux and ELF, but it also works on Darwin and Mach-O. This option also fixes a known problem with LTO on Darwin (https://github.com/google/sanitizers/issues/647). This patch enables the support for Darwin (but still keeps it off by default) and adds the LTO test case.

Differential Revision: https://reviews.llvm.org/D24292

llvm-svn: 281470
2016-09-14 14:06:33 +00:00
James Molloy
69a6bea0ca Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"
This reverts commit r281323. It caused chromium test failures and a selfhost failure.

llvm-svn: 281451
2016-09-14 09:45:28 +00:00
Vassil Vassilev
696a87c99c Missing includes.
llvm-svn: 281450
2016-09-14 08:55:18 +00:00
Tim Northover
aedd29a3b9 GlobalISel: mark pointer stores as legal on AArch64.
llvm-svn: 281448
2016-09-14 08:28:54 +00:00
Sjoerd Meijer
54f48e4444 This reapplies r281304. The issue was that I had missed
to copy the new isAdd field in the tablegen data structure.

llvm-svn: 281447
2016-09-14 08:20:03 +00:00
Elena Demikhovsky
857c15dab1 AVX-512: Fixed a bug in kortest.z intrinsic
Lowering was wrong - X86ISD::SETCC node should return i8 type.

llvm-svn: 281446
2016-09-14 08:06:54 +00:00
Igor Breger
c8f908fbec [AVX512BW] Change truncStore action (v16i16->v16i18). It can be legal only with AVX512VL.
Differential Revision: http://reviews.llvm.org/D24547

llvm-svn: 281445
2016-09-14 08:04:28 +00:00
Craig Topper
33e6517c79 [X86] Remove the VCVTSI2SD32 with rounding intrinsic. It's not used by clang and not needed since 32-bit integer to double is always exact.
llvm-svn: 281442
2016-09-14 06:27:46 +00:00
Wei Mi
c1cf1864f4 Create a getelementptr instead of sub expr for ValueOffsetPair if the
value is a pointer.

This patch is to fix PR30213. When expanding an expr based on ValueOffsetPair,
if the value is of pointer type, we can only create a getelementptr instead
of sub expr.

Differential Revision: https://reviews.llvm.org/D24088

llvm-svn: 281439
2016-09-14 04:39:50 +00:00
Tobias Grosser
672d508b7d Ensure Polly linking works without BUILD_SHARED_LIBS
This change ensures all necessary symbols are resolved correctly. Before this
change on some systems, the linker may have eliminated some symbols not directly
used in bugpoint, but used in Polly.

Suggested-by: Michael Kruse <lvm@meinersbur.de>
llvm-svn: 281438
2016-09-14 03:09:48 +00:00
Peter Collingbourne
db1b5c71be gold: Simplify. Do not unnecessarily enumerate Obj's symbols.
llvm-svn: 281437
2016-09-14 02:55:16 +00:00
Kostya Serebryany
41b41f51a8 [libFuzzer] start using trace-pc-guard as an alternative source of coverage
llvm-svn: 281435
2016-09-14 02:13:06 +00:00
Kostya Serebryany
562a9d7d62 [sanitizer-coverage] add yet another flavour of coverage instrumentation: trace-pc-guard. The intent is to eventually replace all of {bool coverage, 8bit-counters, trace-pc} with just this one. LLVM part
llvm-svn: 281431
2016-09-14 01:39:35 +00:00
Akira Hatanaka
6613b97f48 Address Pete's review comment and define OrigArg on its own line.
This is a follow-up to r281419.

llvm-svn: 281421
2016-09-13 23:53:43 +00:00
Akira Hatanaka
3bd6db7cbf [ObjCARC] Traverse chain downwards to replace uses of argument passed to
ObjC library call with call return.

ARC contraction tries to replace uses of an argument passed to an
objective-c library call with the call return value. For example, in the
following IR, it replaces uses of argument %9 and uses of the values
discovered traversing the chain upwards (%7 and %8) with the call return
%10, if they are dominated by the call to @objc_autoreleaseReturnValue.
This transformation enables code-gen to tail-call the call to
@objc_autoreleaseReturnValue, which is necessary to enable auto release
return value optimization.

%7 = tail call i8* @objc_loadWeakRetained(i8** %6)
%8 = bitcast i8* %7 to %0*
%9 = bitcast %0* %8 to i8*
%10 = tail call i8* @objc_autoreleaseReturnValue(i8* %9)
ret %0* %8

Since r276727, llvm started removing redundant bitcasts and as a result
started feeding the following IR to ARC contraction:

%7 = tail call i8* @objc_loadWeakRetained(i8** %6)
%8 = bitcast i8* %7 to %0*
%9 = tail call i8* @objc_autoreleaseReturnValue(i8* %7)
ret %0* %8

ARC contraction no longer does the optimization described above since it
only traverses the chain upwards and fails to recognize that the
function return can be replaced by the call return. This commit changes
ARC contraction to traverse the chain downwards too and replace uses of
bitcasts with the call return.

rdar://problem/28011339

Differential Revision: https://reviews.llvm.org/D24523

llvm-svn: 281419
2016-09-13 23:43:11 +00:00