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Commit Graph

156715 Commits

Author SHA1 Message Date
Volodymyr Sapsai
befcc521fc [ThinLTO] Fix missing call graph edges for calls with bitcasts.
This change doesn't fix the root cause of the miscompile PR34966 as the root
cause is in the linker ld64. This change makes call graph more complete
allowing to have better module imports/exports.

rdar://problem/35344706

Reviewers: tejohnson

Reviewed By: tejohnson

Subscribers: mehdi_amini, inglorion, eraman, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D39356

llvm-svn: 317853
2017-11-10 00:47:47 +00:00
Bob Haarman
eca6346e71 [support] allocate exact size required for mapping in Support/Windws/Path.inc
Summary:
zturner suggested that mapped_file_region::init() on Windows seems to
create mappings that are larger than they need to be: Offset+Size
instead of Size. Indeed, that appears to be the case. I confirmed that
tests pass with mappings of just Size bytes, and fail with Size-1
bytes, suggesting that Size is indeed the correct value.

Reviewers: amccarth, zturner

Reviewed By: zturner

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D39876

llvm-svn: 317850
2017-11-10 00:17:31 +00:00
Easwaran Raman
5c380db441 [SimplifyCFG] Fix a test case.
This was first committed in r317845, but had the order of branch weights
wrong and didn't properly check the output.

llvm-svn: 317848
2017-11-09 23:17:52 +00:00
Easwaran Raman
f6c9c0313c Add a wrapper function to set branch weights metadata.
Summary:
This wrapper checks if there is at least one non-zero weight before
setting the metadata.

Reviewers: davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39872

llvm-svn: 317845
2017-11-09 22:52:20 +00:00
Sanjay Patel
13489de5da [Reassociate] regenerate test checks; NFC
llvm-svn: 317841
2017-11-09 22:41:39 +00:00
Kostya Serebryany
1433212fd3 [libFuzzer] update links in the docs
llvm-svn: 317837
2017-11-09 21:35:28 +00:00
Kostya Serebryany
e7a55e801f [libFuzzer] update the docs, document how to resume the merge
llvm-svn: 317836
2017-11-09 21:32:02 +00:00
Zachary Turner
d7b0abacde Add a Cross-compilation toolchain file for MSVC.
With this patch, you can now cross-compile for Windows
on non-Windows hosts.

Differential Revision: https://reviews.llvm.org/D39814

This allows cross-compiling for windows on other platforms.

llvm-svn: 317830
2017-11-09 20:38:16 +00:00
Paul Robinson
4494c25a38 Fix out-of-order stepping behavior in programs with hoisted constants.
When the Constant Hoisting pass moves expensive constants into a
common block, it would assign a debug location equal to the last use
of that constant. While this is certainly intuitive, it places the
constant in an out-of-order location, according to the debug location
information. This produces out-of-order stepping when debugging
programs affected by this pass.

This patch creates in-order stepping behavior by merging the debug
locations for hoisted constants, and the new insertion point.

Patch by Matthew Voss!

Differential Revision: https://reviews.llvm.org/D38088

llvm-svn: 317827
2017-11-09 20:01:31 +00:00
Alex Bradbury
b41889c358 [utils] Fix RISC-V support in update_llc_test_checks.py
scrub_asm_riscv now takes two arguments rather than one.

llvm-svn: 317826
2017-11-09 20:01:25 +00:00
Adrian Prantl
d77c420837 Preserve debug info when DAG-combinging (zext (truncate x)) -> (and x, mask).
rdar://problem/27139077

llvm-svn: 317825
2017-11-09 19:50:20 +00:00
Zachary Turner
61d980d677 [Support] Make llvm::Error and Expected faster.
Whenever LLVM_ENABLE_ABI_BREAKING_CHECKS is enabled, which
is usually the case for example when asserts are enabled,
Error's destructor does some additional checking to make sure
that that it does not represent an error condition and that it
was checked.

However, this is -- by definition -- not the likely codepath.
Some profiling shows that at least with some compilers, simply
calling assertIsChecked -- in a release build with full
optimizations -- can account for up to 15% of the entire
runtime of the program, even though this function should almost
literally be a no-op.

The problem is that the assertIsChecked function can be considered
too big to inline depending on the compiler's inliner.  Since it's
unlikely to ever need to failure path though, we can move it out
of line and force it to not be inlined, so that the fast path
can be inlined.

In my test (using lld to link clang with CMAKE_BUILD_TYPE=Release
and LLVM_ENABLE_ASSERTIONS=ON), this reduces link time from 27
seconds to 23.5 seconds, which is a solid 15% gain.

llvm-svn: 317824
2017-11-09 19:31:52 +00:00
Alexey Bataev
827225754a [SLP] Fix PR23510: Try to find best possible vectorizable stores.
Summary:
The analysis of the store sequence goes in straight order - from the
first store to the last. Bu the best opportunity for vectorization will
happen if we're going to use reverse order - from last store to the
first. It may be best because usually users have some initialization
part + further processing and this first initialization may confuse
SLP vectorizer.

Reviewers: RKSimon, hfinkel, mkuper, spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39606

llvm-svn: 317821
2017-11-09 19:07:16 +00:00
Sanjay Patel
4d3a024c41 [Reassociate] auto-generate test checks; NFC
llvm-svn: 317819
2017-11-09 18:26:49 +00:00
Sanjay Patel
96c9de8558 [Reassociate] don't name values "tmp"; NFCI
The toxic stew of created values named 'tmp' and tests that already have
values named 'tmp' and CHECK lines looking for values named 'tmp' causes
bad things to happen in our test line auto-generation scripts because it
wants to use 'TMP' as a prefix for unnamed values. Use less 'tmp' to 
avoid that.

llvm-svn: 317818
2017-11-09 18:14:24 +00:00
Mandeep Singh Grang
73b861566f [GlobalMerge] Stable sort GlobalSets to fix non-deterministic sort order
Summary: This fixes failure in CodeGen/AArch64/global-merge-group-by-use.ll uncovered by D39245.

Reviewers: ab, asl

Reviewed By: ab

Subscribers: aemerson, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D39635

llvm-svn: 317817
2017-11-09 18:05:17 +00:00
Nuno Lopes
a74afab653 revert r317812 [BasicAA] fix build break by converting the previously introduced assert into an if stmt
The code has a bug, but some tests regress.
I'll discuss this further on the mailing list.

llvm-svn: 317815
2017-11-09 17:35:36 +00:00
Nuno Lopes
a2da14871b [BasicAA] fix build break by converting the previously introduced assert into an if stmt
Apparently V1Size == -1 doest imply V2Size == -1, which is a bit surprising to me.

llvm-svn: 317812
2017-11-09 17:06:42 +00:00
Sanjay Patel
e702925699 revert r317809 - [Reassociate] regenerate test checks; NFC
The reassociate pass generates named values such as "%tmp2" which trips up the script's regex's
because the script uses a 'TMP' prefix for unnamed values (%2).

llvm-svn: 317810
2017-11-09 16:46:04 +00:00
Sanjay Patel
ff281bbbbb [Reassociate] regenerate test checks; NFC
llvm-svn: 317809
2017-11-09 16:35:30 +00:00
Ulrich Weigand
c3b7f3ba61 [SystemZ] Add support for the "o" inline asm constraint
We don't really need any special handling of "offsettable"
memory addresses, but since some existing code uses inline
asm statements with the "o" constraint, add support for this
constraint for compatibility purposes.

llvm-svn: 317807
2017-11-09 16:31:57 +00:00
Sanjay Patel
e01649badd [Reassociate] regenerate test checks; NFC
llvm-svn: 317806
2017-11-09 16:30:19 +00:00
Sanjay Patel
d80997844a [Reassociate] add check lines; NFC
llvm-svn: 317805
2017-11-09 16:25:35 +00:00
Sanjay Patel
8be3f3e28c [Reassociate] add tests with 'reassoc' FMF and regenerate checks; NFC
llvm-svn: 317804
2017-11-09 16:23:32 +00:00
Nuno Lopes
ee4f30c74d [BasicAA] add assertion for corner case in aliasGEP()
llvm-svn: 317803
2017-11-09 16:16:46 +00:00
Simon Dardis
49cc1d1c05 [mips] Correct microMIP's jump and add unconditional branch pseudo
Correct the definition of 'j' as being unavailable for microMIPS32R6 and
provide the 'b' assembly idiom for codegen purposes for microMIPS32r3.

Provide the necessary 'br' pattern for microMIPS32R6 as it now longer
incorrectly uses the 'j' instruction.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D39741

llvm-svn: 317801
2017-11-09 16:02:18 +00:00
Alex Bradbury
22a2cefdc7 [RISCV] Re-generate test/CodeGen/RISCV/alu32.ll using update_llc_test_checks.py
No real change, but makes it marginally easier to merge the remainder of the
out-of-tree patches.

llvm-svn: 317796
2017-11-09 15:45:42 +00:00
Alex Bradbury
3b5341d83a [RISCV] MC layer support for the standard RV32A instruction set extension
llvm-svn: 317791
2017-11-09 15:00:03 +00:00
Simon Pilgrim
01cbd4e4bf Fix 'not all control paths return a value' warning on MSVC builds
llvm-svn: 317790
2017-11-09 14:56:17 +00:00
Dave Lee
dca7f2c601 Reapply: Allow yaml2obj to order implicit sections for ELF
Summary:
This change allows yaml input to control the order of implicitly added sections
(`.symtab`, `.strtab`, `.shstrtab`). The order is controlled by adding a
placeholder section of the given name to the Sections field.

This change is to support changes in D39582, where it is desirable to control
the location of the `.dynsym` section.

This reapplied version fixes:
  1. use of a function call within an assert
  2. failing lld test which has an unnamed section
  3. incorrect section count when given an unnamed section

Additionally, one more test to cover the unnamed section failure.

Reviewers: compnerd, jakehehrlich

Reviewed By: jakehehrlich

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39749

llvm-svn: 317789
2017-11-09 14:53:43 +00:00
Alex Bradbury
284dc625a5 [RISCV] MC layer support for the standard RV32M instruction set extension
llvm-svn: 317788
2017-11-09 14:46:30 +00:00
Andrew V. Tischenko
c2204901e8 Sched model improving on btver2: JFPU01 resource, vtestp* for xmm.
Differential Revision: https://reviews.llvm.org/D39802

llvm-svn: 317785
2017-11-09 14:19:59 +00:00
Andrew V. Tischenko
1297e99623 Add -print-schedule scheduling comments to inline asm.
Differential Revision: https://reviews.llvm.org/D39728

llvm-svn: 317782
2017-11-09 12:45:40 +00:00
Craig Topper
4f63d7a01e [X86] Give priority to EVEX FMA instructions over FMA4 instructions.
No existing processor has both so it doesn't really matter what we do here. But we were previously just relying on pattern order which gave FMA4 priority.

llvm-svn: 317775
2017-11-09 08:26:26 +00:00
Vitaly Buka
c723f0c225 Fix "default label in switch which covers all enumeration values" warning
llvm-svn: 317771
2017-11-09 07:46:13 +00:00
Sanjoy Das
31aae253dc [SectionMemoryManager] Abstract out mmap, munmap, mprotect even more ; NFC
Summary:
This will let ORC JIT clients plug in custom logic for the mmap, munmap and
mprotect paths.

Reviewers: loladiro, dblaikie

Subscribers: mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D39300

llvm-svn: 317770
2017-11-09 06:31:33 +00:00
Craig Topper
6753f35627 [X86] Make X86ISD::FMADDS3 isel patterns commutable.
This was missed when FMADDS3 was split from X86ISD::FMADDS3_RND.

llvm-svn: 317769
2017-11-09 06:17:05 +00:00
Serguei Katkov
b6e03dbb87 [GVN PRE] Patch the source for Phi node in PRE
We must patch all existing incoming values of Phi node,
otherwise it is possible that we can see poison
where program does not expect to see it.

This is the similar what GVN does.

The added test test/Transforms/GVN/PRE/pre-jt-add.ll shows an
example of wrong optimization done by jump threading due to
GVN PRE did not patch existing incoming value.

Reviewers: mkazantsev, wmi, dberlin, davide
Reviewed By: dberlin
Subscribers: efriedma, llvm-commits
Differential Revision: https://reviews.llvm.org/D39637

llvm-svn: 317768
2017-11-09 06:02:18 +00:00
Craig Topper
ef6d65ff72 [X86] Rename the VEX scalar fma builtins to end with a '3' to match gcc
I think we need to use different builtins for the FMA4 instructions since those instructions zero the upper bits and FMA3 instructions pass the bits through.

So this moves the existing builtins to be the FMA3 versions. New versions will be added for FMA4.

llvm-svn: 317765
2017-11-09 04:10:42 +00:00
Vedant Kumar
2ce6afbd1a [llvm-cov] Fix more -path-equivalence test bugs
llvm-svn: 317764
2017-11-09 02:50:24 +00:00
Vedant Kumar
7cea1a40a3 [llvm-cov] Fix a -path-equivalence bug in a test
llvm-svn: 317763
2017-11-09 02:42:34 +00:00
Vedant Kumar
59fa2fd04c [llvm-cov] Don't render empty region marker lines
This fixes an issue where llvm-cov prints an empty line, thinking it
needs to display region markers, when it actually doesn't.

llvm-svn: 317762
2017-11-09 02:33:44 +00:00
Vedant Kumar
8efae3e054 [Coverage] Use the wrapped segment when a line has entry segments
We've worked around bugs in the frontend by ignoring the count from
wrapped segments when a line has at least one region entry segment.
Those frontend bugs are now fixed, so it's time to regenerate the
checked-in covmapping files and remove the workaround.

llvm-svn: 317761
2017-11-09 02:33:43 +00:00
Marek Olsak
72631b54b3 AMDGPU: Merge BUFFER_STORE_DWORD_OFFEN/OFFSET into x2, x4
Summary:
Only 56 shaders (out of 48486) are affected.

Totals from affected shaders (changed stats only):
SGPRS: 2420 -> 2460 (1.65 %)
Spilled VGPRs: 94 -> 112 (19.15 %)
Scratch size: 524 -> 528 (0.76 %) dwords per thread
Code Size: 187400 -> 184992 (-1.28 %) bytes

One DiRT Showdown shader spills 6 more VGPRs.
One Grid Autosport shader spills 12 more VGPRs.

The other 54 shaders only have a decrease in code size.
(I'm ignoring the SGPR noise)

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D39012

llvm-svn: 317755
2017-11-09 01:52:55 +00:00
Marek Olsak
3170d60e41 AMDGPU: Lower buffer store and atomic intrinsics manually
Summary:
Without this, SIMemoryLegalizer inserts s_waitcnt vmcnt(0) before every
buffer store and atomic instruction.

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D39060

llvm-svn: 317754
2017-11-09 01:52:48 +00:00
Marek Olsak
fd39065f1d AMDGPU: Merge BUFFER_LOAD_DWORD_OFFSET into x2, x4
Summary: Only 3 (out of 48486) shaders are affected.

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D38951

llvm-svn: 317753
2017-11-09 01:52:36 +00:00
Marek Olsak
2bb24b05c7 AMDGPU: Merge BUFFER_LOAD_DWORD_OFFEN into x2, x4
Summary:
-9.9% code size decrease in affected shaders.

Totals (changed stats only):
SGPRS: 2151462 -> 2170646 (0.89 %)
VGPRS: 1634612 -> 1640288 (0.35 %)
Spilled SGPRs: 8942 -> 8940 (-0.02 %)
Code Size: 52940672 -> 51727288 (-2.29 %) bytes
Max Waves: 373066 -> 371718 (-0.36 %)

Totals from affected shaders:
SGPRS: 283520 -> 302704 (6.77 %)
VGPRS: 227632 -> 233308 (2.49 %)
Spilled SGPRs: 3966 -> 3964 (-0.05 %)
Code Size: 12203080 -> 10989696 (-9.94 %) bytes
Max Waves: 44070 -> 42722 (-3.06 %)

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D38950

llvm-svn: 317752
2017-11-09 01:52:30 +00:00
Marek Olsak
fcc32542ea AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4
Summary:
Only constant offsets (*_IMM opcodes) are merged.
It reuses code for LDS load/store merging.
It relies on the scheduler to group loads.

The results are mixed, I think they are mostly positive. Most shaders are
affected, so here are total stats only:

 SGPRS: 2072198 -> 2151462 (3.83 %)
 VGPRS: 1628024 -> 1634612 (0.40 %)
 Spilled SGPRs: 7883 -> 8942 (13.43 %)
 Spilled VGPRs: 97 -> 101 (4.12 %)
 Scratch size: 1488 -> 1492 (0.27 %) dwords per thread
 Code Size: 60222620 -> 52940672 (-12.09 %) bytes
 Max Waves: 374337 -> 373066 (-0.34 %)

There is 13.4% increase in SGPR spilling, DiRT Showdown spills a few more
VGPRs (now 37), but 12% decrease in code size.

These are the new stats for SGPR spilling. We already spill a lot SGPRs,
so it's uncertain whether more spilling will make any difference since
SGPRs are always spilled to VGPRs:

 SGPR SPILLING APPS   Shaders SpillSGPR AvgPerSh
 alien_isolation         2938       100      0.0
 batman_arkham_origins    589         6      0.0
 bioshock-infinite       1769         4      0.0
 borderlands2            3968        22      0.0
 counter_strike_glob..   1142        60      0.1
 deus_ex_mankind_div..   1410        79      0.1
 dirt-showdown            533         4      0.0
 dirt_rally               364      1163      3.2
 divinity                1052         2      0.0
 dota2                   1747         7      0.0
 f1-2015                  776      1515      2.0
 grid_autosport          1767      1505      0.9
 hitman                  1413       273      0.2
 left_4_dead_2           1762         4      0.0
 life_is_strange         1296        26      0.0
 mad_max                  358        96      0.3
 metro_2033_redux        2670        60      0.0
 payday2                 1362        22      0.0
 portal                   474         3      0.0
 saints_row_iv           1704         8      0.0
 serious_sam_3_bfe        392      1348      3.4
 shadow_of_mordor        1418        12      0.0
 shadow_warrior          3956       239      0.1
 talos_principle          324      1735      5.4
 thea                     172        17      0.1
 tomb_raider             1449       215      0.1
 total_war_warhammer      242        56      0.2
 ue4_effects_cave         295        55      0.2
 ue4_elemental            572        12      0.0
 unigine_tropics          210        56      0.3
 unigine_valley           278       152      0.5
 victor_vran             1262        84      0.1
 yofrankie                 82         2      0.0

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D38949

llvm-svn: 317751
2017-11-09 01:52:23 +00:00
Marek Olsak
438fa3e3f9 AMDGPU: Fold immediate offset into BUFFER_LOAD_DWORD lowered from SMEM
Summary:
-5.3% code size in affected shaders.

Changed stats only:

48486 shaders in 30489 tests
Totals:
SGPRS: 2086406 -> 2072430 (-0.67 %)
VGPRS: 1626872 -> 1627960 (0.07 %)
Spilled SGPRs: 7865 -> 7912 (0.60 %)
Code Size: 60978060 -> 60188764 (-1.29 %) bytes
Max Waves: 374530 -> 374342 (-0.05 %)

Totals from affected shaders:
SGPRS: 299664 -> 285688 (-4.66 %)
VGPRS: 233844 -> 234932 (0.47 %)
Spilled SGPRs: 3959 -> 4006 (1.19 %)
Code Size: 14905272 -> 14115976 (-5.30 %) bytes
Max Waves: 46202 -> 46014 (-0.41 %)

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D38915

llvm-svn: 317750
2017-11-09 01:52:17 +00:00
Craig Topper
f7a8beb9b6 [X86] Make sure we don't read too many operands from X86ISD::FMADDS1/FMADDS3 nodes when doing FNEG combine.
r317453 added new ISD nodes without rounding modes that were added to an existing if/else chain. But all the previous nodes handled there included a rounding mode. The final code after this if/else chain expected an extra operand that isn't present for the new nodes.

llvm-svn: 317748
2017-11-09 01:06:47 +00:00