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228 Commits

Author SHA1 Message Date
Matt Arsenault
0cbe5b2357 R600/SI: Fix div_scale intrinsic. 
The operand that must match one of the others does matter,
and implement selecting for it.

llvm-svn: 211523
 2014-06-23 18:28:28 +00:00
Tom Stellard
ae7faa387d R600/SI: Add patterns for ctpop inside a branch 
llvm-svn: 211378
 2014-06-20 17:06:11 +00:00
Tom Stellard
2d56aec1cd R600/SI: Add a pattern for f32 ftrunc 
llvm-svn: 211377
 2014-06-20 17:06:09 +00:00
Tom Stellard
d4aa49ad5e R600/SI: Add a VALU pattern for i64 xor 
llvm-svn: 211373
 2014-06-20 17:05:57 +00:00
Matt Arsenault
b82983ef6a R600/SI: Add intrinsics for various math instructions. 
These will be used for custom lowering and for library
implementations of various math functions, so it's useful
to expose these as builtins.

llvm-svn: 211247
 2014-06-19 01:19:19 +00:00
Marek Olsak
d80d0ca951 R600/SI: add gather4 and getlod intrinsics (v3) 
This contains all the previous patches + getlod support on top of it.
It doesn't use SDNodes anymore, so it's quite small.
It also adds v16i8 to SReg_128, which is used for the sampler descriptor.

Reviewed-by: Tom Stellard
llvm-svn: 211228
 2014-06-18 22:00:29 +00:00
Matt Arsenault
a46ba4c9d1 R600/SI: Add intrinsics for brev instructions 
llvm-svn: 211187
 2014-06-18 17:13:57 +00:00
Matt Arsenault
dc16a24358 R600/SI: Comparisons set vcc. 
llvm-svn: 211178
 2014-06-18 16:53:48 +00:00
Matt Arsenault
508925b13a R600/SI: Match cttz_zero_undef 
llvm-svn: 211116
 2014-06-17 17:36:27 +00:00
Matt Arsenault
71fb43e88e R600/SI: Match ctlz_zero_undef 
llvm-svn: 211115
 2014-06-17 17:36:24 +00:00
Tom Stellard
a529beed9c R600: Use LDS and vectors for private memory 
llvm-svn: 211110
 2014-06-17 16:53:14 +00:00
Tom Stellard
4bdc400436 R600/SI: Add a pattern for llvm.AMDGPU.barrier.global 
llvm-svn: 211109
 2014-06-17 16:53:09 +00:00
Tom Stellard
cc6701010d R600: Remove AMDIL instruction and register definitions 
Most of these are no longer used any more.

llvm-svn: 210915
 2014-06-13 16:38:59 +00:00
Matt Arsenault
e19ddbd0dc R600: Mostly remove remaining AMDIL intrinsics. 
Delete all unused ones, and add new AMDGPU named intrinsics for
the ones that are. Handle the old AMDIL names for comptability (although
remove their GCCBuiltin names) and add tests since there weren't any
for these before.

llvm-svn: 210827
 2014-06-12 21:15:44 +00:00
Matt Arsenault
2c82883c7a R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec* 
There is not such thing as a 0-data ds instruction, and the data
operand needs to be a vgpr set to something meaningful.

llvm-svn: 210756
 2014-06-12 08:21:54 +00:00
Matt Arsenault
b6b9bb5978 R600/SI: Fix bitcast between v2i32 and f64 
This is the same problem fixed in r210664 for more types.

The test passes without this fix. For some reason
I'm only hitting this when creating selects lowered
to v2i32 selects.

llvm-svn: 210692
 2014-06-11 19:31:13 +00:00
Matt Arsenault
b8a7faa150 R600/SI: Update place using old subtarget predicate 
llvm-svn: 210683
 2014-06-11 18:11:34 +00:00
Matt Arsenault
33d239c3a3 R600/SI: Add common 64-bit LDS atomics 
llvm-svn: 210680
 2014-06-11 18:08:54 +00:00
Matt Arsenault
90d1f4fc84 R600/SI: Add instruction definitions for 64-bit LDS atomics 
llvm-svn: 210679
 2014-06-11 18:08:50 +00:00
Matt Arsenault
ffa54309ef R600/SI: Add 32-bit LDS atomic cmpxchg 
llvm-svn: 210678
 2014-06-11 18:08:48 +00:00
Matt Arsenault
5784f403fd R600/SI: Use LDS atomic inc / dec 
llvm-svn: 210677
 2014-06-11 18:08:45 +00:00
Matt Arsenault
3067074b27 R600/SI: Add other LDS atomic operations 
llvm-svn: 210676
 2014-06-11 18:08:42 +00:00
Matt Arsenault
c187b34585 R600/SI: Add instruction definitions for more LDS ops 
llvm-svn: 210675
 2014-06-11 18:08:39 +00:00
Matt Arsenault
e633c2eeb6 R600/SI: Fix backwards names for local atomic instructions. 
The manual lists them as *_RTN_U32, not *_U32_RTN, which is more
consistent with how every other sized instruction is named.

llvm-svn: 210674
 2014-06-11 18:08:37 +00:00
Matt Arsenault
174782d2e9 R600/SI: Refactor local atomics. 
Use patterns that will also match the immediate offset to
match the normal read / writes.

llvm-svn: 210673
 2014-06-11 18:08:34 +00:00
Matt Arsenault
a75d166beb R600/SI: Use v_cvt_f32_ubyte* instructions 
This eliminates extra extract instructions when loading an i8 vector to
a float vector.

llvm-svn: 210666
 2014-06-11 17:50:44 +00:00
Matt Arsenault
52e8d9b98d R600/SI: Fix selection failure on scalar_to_vector 
There seem to be only 2 places that produce these,
and it's kind of tricky to hit them.

Also fixes failure to bitcast between i64 and v2f32,
although this for some reason wasn't actually broken in the
simple bitcast testcase, but did in the scalar_to_vector one.

llvm-svn: 210664
 2014-06-11 17:40:32 +00:00
Tom Stellard
ba8f206726 R600/SI: Fix a crash when spilling SGPRs 
We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.

This fixes a crash in the game Antichamber.

https://bugs.freedesktop.org/show_bug.cgi?id=75276

llvm-svn: 210587
 2014-06-10 21:20:38 +00:00
Matt Arsenault
6387e9a3dc R600/SI: Implement i64 ctpop 
llvm-svn: 210568
 2014-06-10 19:18:24 +00:00
Matt Arsenault
8407076508 R600/SI: Use bcnt instruction for ctpop 
llvm-svn: 210567
 2014-06-10 19:18:21 +00:00
Matt Arsenault
d30b483e1a R600: Handle fcopysign 
llvm-svn: 210564
 2014-06-10 19:00:20 +00:00
Matt Arsenault
5bfef73e00 R600/SI: Handle sign_extend and zero_extend to i64 with patterns. 
llvm-svn: 210563
 2014-06-10 18:54:59 +00:00
Matt Arsenault
f38f9f9399 R600/SI: Rename VOP3 helper class to be more general 
It has other uses besides shift instructions.

llvm-svn: 210478
 2014-06-09 17:00:46 +00:00
Matt Arsenault
c9f3bd4d6c R600/SI: Keep 64-bit not on SALU 
llvm-svn: 210476
 2014-06-09 16:36:31 +00:00
Matt Arsenault
9e400b2e26 R600/SI: Match rsq instructions 
llvm-svn: 210226
 2014-06-05 00:15:55 +00:00
Matt Arsenault
1c23cf5566 R600/SI: Remove redundant patterns 
These patterns are already handled in the instruction definition.

llvm-svn: 209979
 2014-05-31 19:25:17 +00:00
Matt Arsenault
ff3cea9ab5 R600/SI: Fix [s|u]int_to_fp for i1 
llvm-svn: 209971
 2014-05-31 06:47:42 +00:00
Matt Arsenault
0f46ee15d3 R600/SI: Fix pattern variable names. 
These are confusing enough since the order swaps,
so give them more useful names.

llvm-svn: 209787
 2014-05-29 01:18:01 +00:00
Matt Arsenault
e43426533f R600: Add intrinsics for mad24 
llvm-svn: 209456
 2014-05-22 18:00:15 +00:00
Matt Arsenault
8c8ff09456 R600/SI: Move instruction pattern to instruction definition 
llvm-svn: 209454
 2014-05-22 17:45:20 +00:00
Matt Arsenault
cec6ae49e8 R600/SI: Match fp_to_uint / uint_to_fp for f64 
llvm-svn: 209388
 2014-05-22 03:20:30 +00:00
Tom Stellard
a6f7eff1ad R600/SI: Refactor the VOP3_32 tablegen class 
This will allow us to use a single MachineInstr to represent
instructions which behave the same but have different encodings
on some subtargets.

llvm-svn: 209028
 2014-05-16 20:56:47 +00:00
Tom Stellard
724f41cd91 R600/SI: Add a PredicateControl class for managing TableGen predicates 
This was inspired by the PredicateControl class in the MIPS backend.

llvm-svn: 209027
 2014-05-16 20:56:45 +00:00
Tom Stellard
dd51c2b7f4 R600/SI: Move tablegen patterns away from instruction defs 
llvm-svn: 209026
 2014-05-16 20:56:44 +00:00
Tom Stellard
caa7274fef R600/SI: Remove unused instruction 
llvm-svn: 209025
 2014-05-16 20:56:43 +00:00
Tom Stellard
2022c1eb1b R600/SI: Promote f32 SELECT to i32 
llvm-svn: 209024
 2014-05-16 20:56:41 +00:00
Tom Stellard
9ed79b238d R600/SI: Remove duplicate pattern 
llvm-svn: 209023
 2014-05-16 20:56:37 +00:00
Tom Stellard
dbf9b9b7af R600/SI: Stop using VSrc_* as the default register class for types. 
We now use SReg_* for integer types and VReg_* for floating-point types.
This should help simplify the SIFixSGPRCopies pass and no longer causes
ISel to insert a COPY after termiator instuctions that output a value.

This change is covered by exisitng tests.

llvm-svn: 208888
 2014-05-15 14:41:57 +00:00
Tom Stellard
efb8470c62 R600/SI: Use VALU instructions for i1 ops 
llvm-svn: 208885
 2014-05-15 14:41:50 +00:00
Vincent Lejeune
840594f1e6 R600/SI: Prettier display of input modifiers 
llvm-svn: 208479
 2014-05-10 19:18:33 +00:00