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Author SHA1 Message Date
Justin Holewinski
f86bf451e4 PTX: Attempt to cleanup/unify the handling of FP rounding modes. This requires 
us to manually provide Pat<> definitions for all FP instruction patterns.

llvm-svn: 140849
 2011-09-30 12:54:43 +00:00
Torok Edwin
10dcb27bb4 Instead of crashing when MCAsmInfo is NULL, add an assert. 
This helps with porting code from 2.9 to 3.0 as TargetSelect.h changed location,
and if you include the old one by accident you will trigger this assert.

llvm-svn: 140848
 2011-09-30 12:31:57 +00:00
Akira Hatanaka
dcd69c2e07 Mips64 shift instructions. 
llvm-svn: 140841
 2011-09-30 03:18:46 +00:00
Akira Hatanaka
4bdb4b1958 Mips64 arithmetic and logical instructions with one source register and 
immediate.

llvm-svn: 140839
 2011-09-30 02:08:54 +00:00
Jim Grosbach
d94ffffc87 ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. 
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834
 2011-09-30 00:50:06 +00:00
Jakob Stoklund Olesen
82a55057c4 Precompute a bit vector of register sub-classes. 
llvm-svn: 140827
 2011-09-30 00:10:40 +00:00
Jakob Stoklund Olesen
35c649f61b Order register classes topologically. 
All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.

This will be used to simplify some sub-class operations.

llvm-svn: 140826
 2011-09-30 00:10:36 +00:00
Akira Hatanaka
50a4f6d570 Fill delay slot with useful instructions. Modified from Sparc's version of delay 
slot filler.

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140825
 2011-09-29 23:52:13 +00:00
Bill Wendling
ee48218f94 Create a machine basic block in the constant pool and retrieve the symbol for an MBB. 
llvm-svn: 140824
 2011-09-29 23:50:42 +00:00
Bill Wendling
de36760902 Support creating a constant pool value for a machine basic block. 
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.

llvm-svn: 140823
 2011-09-29 23:48:44 +00:00
Nick Lewycky
fc476a3d3f Fold two identical set lookups into one. No functionality change. 
llvm-svn: 140821
 2011-09-29 23:40:12 +00:00
Jakob Stoklund Olesen
d7b6708541 Switch to ArrayRef<CodeGenRegisterClass*>. 
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

llvm-svn: 140816
 2011-09-29 22:28:37 +00:00
Dan Gohman
7dca165e93 When eliminating unnecessary retain+autorelease on return values, 
handle the case where the retain is in a different basic block.
rdar://10210274.

llvm-svn: 140815
 2011-09-29 22:27:34 +00:00
Dan Gohman
2df048a94b Don't eliminate objc_retainBlock calls on stack objects if the 
objc_retainBlock call is potentially responsible for copying
the block to the heap to extend its lifetime. rdar://10209613.

llvm-svn: 140814
 2011-09-29 22:25:23 +00:00
Jim Grosbach
2e78f4835d Tidy up. Formatting. 
llvm-svn: 140810
 2011-09-29 21:43:01 +00:00
Nick Lewycky
73dbedf97e Fix typo. 
llvm-svn: 140807
 2011-09-29 21:07:46 +00:00
Akira Hatanaka
70be05d5d0 Mips64 arithmetic and logical instructions with two source registers. 
llvm-svn: 140806
 2011-09-29 20:37:56 +00:00
Eli Friedman
ac33381aa1 Clean up uses of switch instructions so they are not dependent on the operand ordering. Patch by Stepan Dyatkovskiy. 
llvm-svn: 140803
 2011-09-29 20:21:17 +00:00
Devang Patel
e5a1e5b655 Simplify. 
llvm-svn: 140789
 2011-09-29 17:06:40 +00:00
Devang Patel
b1bef6ba30 Clarify comments. 
llvm-svn: 140787
 2011-09-29 16:52:53 +00:00
Devang Patel
0729c18444 Remove unnecessary and unused data member. 
llvm-svn: 140786
 2011-09-29 16:48:44 +00:00
Devang Patel
204df6030c Cosmetic changes, as per Nick's review. 
llvm-svn: 140785
 2011-09-29 16:46:47 +00:00
Duncan Sands
fbf3eb2e3e Place this bracket according to the LLVM style. 
llvm-svn: 140784
 2011-09-29 16:01:46 +00:00
Justin Holewinski
e429b56306 PTX: Fix broken shared library build 
llvm-svn: 140783
 2011-09-29 14:25:48 +00:00
Jakob Stoklund Olesen
76da38e8e8 Expand the x86 V_SET0* pseudos right after register allocation. 
This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.

llvm-svn: 140776
 2011-09-29 05:10:54 +00:00
NAKAMURA Takumi
f82662e1f6 Target/ARM: Unbreak! CMake! Build! 
llvm-svn: 140774
 2011-09-29 03:32:49 +00:00
Jakob Stoklund Olesen
a2a0ba4d56 Delete NEONMoveFix, now unused. 
llvm-svn: 140773
 2011-09-29 02:56:45 +00:00
Jakob Stoklund Olesen
cfd5280df5 Use ExecutionDepsFix instead of NEONMoveFix. 
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.

llvm-svn: 140772
 2011-09-29 02:48:41 +00:00
Andrew Trick
fa2c108a22 typo + pasto 
llvm-svn: 140769
 2011-09-29 01:53:08 +00:00
Jakob Stoklund Olesen
49803374a4 Remove NumImplicitOps which is now unused. 
llvm-svn: 140767
 2011-09-29 01:47:36 +00:00
Andrew Trick
e1d5ae73ac LSR: rewrite inner loops only. 
Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.

llvm-svn: 140762
 2011-09-29 01:33:38 +00:00
Andrew Trick
75c6a45d08 whitespace 
llvm-svn: 140761
 2011-09-29 01:31:48 +00:00
Andrew Trick
3f3416249a Fix build failures better. 
llvm-svn: 140758
 2011-09-29 01:22:31 +00:00
Daniel Dunbar
8b3e105420 Fix build failure. 
llvm-svn: 140755
 2011-09-29 01:14:42 +00:00
Bill Wendling
cc7e50a465 Move to ISelLowering. 
llvm-svn: 140754
 2011-09-29 01:13:55 +00:00
Justin Holewinski
4966d44b44 PTX: Add new patterns for bitconvert and any_extend 
llvm-svn: 140753
 2011-09-29 01:13:12 +00:00
Michael J. Spencer
3b747b0b5d llvm-size: Apply Chris's code review fixes. 
This doesn't use formated_raw_ostream because it doesn't support the
functionality needed.

llvm-svn: 140751
 2011-09-29 00:59:18 +00:00
Eric Christopher
70718394df Use the local we already set up. 
llvm-svn: 140745
 2011-09-29 00:50:59 +00:00
Jakob Stoklund Olesen
93b4947cff Rewrite MachineInstr::addOperand() to avoid NumImplicitOps. 
The function needs to scan the implicit operands anyway, so no
performance is won by caching the number of implicit operands added to
an instruction.

This also fixes a bug when adding operands after an implicit operand has
been added manually.  The NumImplicitOps count wasn't kept up to date.

MachineInstr::addOperand() will now consistently place all explicit
operands before all the implicit operands, regardless of the order they
are added.  It is possible to change an MI opcode and add additional
explicit operands.  They will be inserted before any existing implicit
operands.

The only exception is inline asm instructions where operands are never
reordered.  This is because of a hack that marks explicit clobber regs
on inline asm as <implicit-def> to please the fast register allocator.
This hack can go away when InstrEmitter and FastIsel can add exact
<dead> flags to physreg defs.

llvm-svn: 140744
 2011-09-29 00:40:51 +00:00
Daniel Dunbar
d499233312 tblgen/ClangDiagnostics: Add support for split default warning "no-werror" and 
"show-in-system-header" bits, which I will be adding in Clang shortly.

llvm-svn: 140741
 2011-09-29 00:29:04 +00:00
Jakob Stoklund Olesen
6cb1647b24 Revert r140731, "Define classes for unary and binary FP instructions and use them to define" 
It broke the unit tests.  Please reapply with tests fixed.

llvm-svn: 140735
 2011-09-28 23:59:28 +00:00
Evan Cheng
1e53900b70 Tighten a ARM dag combine condition to avoid an identity transformation, which 
ends up introducing a cycle in the DAG.

rdar://10196296

llvm-svn: 140733
 2011-09-28 23:16:31 +00:00
Akira Hatanaka
be2c5236ec Define classes for unary and binary FP instructions and use them to define 
multiclasses.

llvm-svn: 140731
 2011-09-28 21:58:01 +00:00
Bill Wendling
e26a78c400 Have the SjLjEHPrepare pass do some more heavy lifting. 
Upon further review, most of the EH code should remain written at the IR
level. The part which breaks SSA form is the dispatch table, so that part will
be moved to the back-end.

llvm-svn: 140730
 2011-09-28 21:56:53 +00:00
Michael J. Spencer
4dc1ab6c03 Fix cast. 
llvm-svn: 140726
 2011-09-28 21:24:44 +00:00
Eli Friedman
81fc13efd2 PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them. 
llvm-svn: 140723
 2011-09-28 21:00:25 +00:00
Michael J. Spencer
3e283fe7d4 Add llvm-size. 
llvm-svn: 140722
 2011-09-28 20:57:46 +00:00
Michael J. Spencer
5948c3822e Object: Add isSection{Data,BSS}. 
llvm-svn: 140721
 2011-09-28 20:57:30 +00:00
Eli Friedman
3b5162de17 NULL cannot be portably used as the last argument to a function with __attribute((sentinel)), even though it usually works. Use (void*)0 instead. PR11002. 
llvm-svn: 140720
 2011-09-28 20:41:50 +00:00
Bill Wendling
2400aacfb7 Perform the lowering only if there are invokes. 
llvm-svn: 140719
 2011-09-28 20:29:45 +00:00