RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 03:53:04 +02:00
Code Issues Projects Releases Wiki Activity
68,584 Commits 4 Branches 5 Tags 704 MiB
f897a6bb16
Commit Graph

68584 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Bill Wendling
f897a6bb16 Default to armv7 instead of armv6. 
llvm-svn: 122457
 2010-12-23 00:49:18 +00:00
Jim Grosbach
b0e9926c33 Trailing whitespace. 
llvm-svn: 122456
 2010-12-22 23:26:02 +00:00
Benjamin Kramer
49942a90b7 DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is illegal. The latter usually compiles into smaller code. 
example code:
unsigned foo(unsigned x, unsigned y) {
  if (x != 0) y--;
  return y;
}

before:
  _foo:                           ## @foo
    cmpl  $1, 4(%esp)             ## encoding: [0x83,0x7c,0x24,0x04,0x01]
    sbbl  %eax, %eax              ## encoding: [0x19,0xc0]
    notl  %eax                    ## encoding: [0xf7,0xd0]
    addl  8(%esp), %eax           ## encoding: [0x03,0x44,0x24,0x08]
    ret                           ## encoding: [0xc3]

after:
  _foo:                           ## @foo
    cmpl  $1, 4(%esp)             ## encoding: [0x83,0x7c,0x24,0x04,0x01]
    movl  8(%esp), %eax           ## encoding: [0x8b,0x44,0x24,0x08]
    adcl  $-1, %eax               ## encoding: [0x83,0xd0,0xff]
    ret                           ## encoding: [0xc3]

llvm-svn: 122455
 2010-12-22 23:17:45 +00:00
Benjamin Kramer
27d13684f5 InstCombine: creating selects from -1 and 0 is fine, they combine into a sext from i1. 
llvm-svn: 122453
 2010-12-22 23:12:15 +00:00
Benjamin Kramer
d8387aa9bd X86: Lower a select directly to a setcc_carry if possible. 
int test(unsigned long a, unsigned long b) { return -(a < b); }
compiles to
  _test:                              ## @test
    cmpq  %rsi, %rdi                  ## encoding: [0x48,0x39,0xf7]
    sbbl  %eax, %eax                  ## encoding: [0x19,0xc0]
    ret                               ## encoding: [0xc3]
instead of
  _test:                              ## @test
    xorl  %ecx, %ecx                  ## encoding: [0x31,0xc9]
    cmpq  %rsi, %rdi                  ## encoding: [0x48,0x39,0xf7]
    movl  $-1, %eax                   ## encoding: [0xb8,0xff,0xff,0xff,0xff]
    cmovael %ecx, %eax                ## encoding: [0x0f,0x43,0xc1]
    ret                               ## encoding: [0xc3]

llvm-svn: 122451
 2010-12-22 23:09:28 +00:00
Rafael Espindola
9e462b3734 Add r122359 back now that the bug in MCDwarfLineAddrFragment fragment has been 
fixed.

llvm-svn: 122448
 2010-12-22 22:16:24 +00:00
Dan Gohman
db69a33d9f Constify. 
llvm-svn: 122447
 2010-12-22 22:10:08 +00:00
Rafael Espindola
3897d5e658 Assert that the AddrDelta expression is really constant and wrap it in a set 
if we have a lame assembler.

llvm-svn: 122446
 2010-12-22 22:04:28 +00:00
Jakob Stoklund Olesen
f761c75efb When RegAllocGreedy decides to spill the interferences of the current register, 
pick the victim with the lowest total spill weight.

llvm-svn: 122445
 2010-12-22 22:01:30 +00:00
Jakob Stoklund Olesen
71e527ef4b Include a shadow of the original CFG edges in the edge bundle graph. 
llvm-svn: 122444
 2010-12-22 22:01:28 +00:00
Rafael Espindola
81ac7c5fad Rename NeedsSetToChangeDiffSize to HasAggressiveSymbolFolding which is a much 
better name and matches what is used in the MachO writer.

llvm-svn: 122443
 2010-12-22 21:51:29 +00:00
Daniel Dunbar
e6ec0e7149 MC/Mach-O/ARM: Don't try to use scattered relocs for BR24 fixups. 
llvm-svn: 122441
 2010-12-22 21:26:43 +00:00
Rafael Espindola
5004de4d8b Add reduced test from 8845. 
llvm-svn: 122438
 2010-12-22 21:15:13 +00:00
Rafael Espindola
6baac40d13 Revert r122359 while I debug PR8845. 
llvm-svn: 122427
 2010-12-22 19:05:49 +00:00
Matt Beaumont-Gay
2a54f466cf Fix another conditional expression mismatched enum type warning. 
llvm-svn: 122419
 2010-12-22 18:25:55 +00:00
Duncan Sands
68d969c2f5 When determining whether the new instruction was already present in 
the original instruction, half the cases were missed (making it not
wrong but suboptimal).  Also correct a typo (A <-> B) in the second
chunk. 

llvm-svn: 122414
 2010-12-22 17:15:25 +00:00
Duncan Sands
e1522867e6 Make this test not depend on how the variable is named. 
llvm-svn: 122413
 2010-12-22 17:08:04 +00:00
Daniel Dunbar
cb8ac619a2 MC/Mach-O/ARM: We always use the SECTDIFF reloc type on ARM, which is 
esp. important given that the LOCAL_SECTDIFF enumeration got redefined.

llvm-svn: 122412
 2010-12-22 16:52:19 +00:00
Daniel Dunbar
63f7a3a108 MC/Mach-O/ARM: Clone off an ARM version of RecordScatteredRelocation until I figure out how it is supposed to work. 
llvm-svn: 122410
 2010-12-22 16:45:29 +00:00
Daniel Dunbar
985567aebc MC/Mach-O: Return to reporting errors if we see unexpected fixup kinds. 
llvm-svn: 122409
 2010-12-22 16:32:41 +00:00
Daniel Dunbar
d85743ca7a MC/Mach-O/ARM: Recognize generic _Data_N fixup kinds. 
llvm-svn: 122408
 2010-12-22 16:32:37 +00:00
Daniel Dunbar
e44a2c1166 MC/Mach-O/ARM: Add enough relocation logic to get BR24 relocations. 
llvm-svn: 122407
 2010-12-22 16:19:24 +00:00
Daniel Dunbar
55eff2421b MC/Mach-O/ARM: Fix thinko. 
llvm-svn: 122406
 2010-12-22 16:19:20 +00:00
Rafael Espindola
c05eac148d Use references and simplify. 
llvm-svn: 122405
 2010-12-22 16:11:57 +00:00
Rafael Espindola
7c995a90fc Simplify the handling of .size expressions. 
llvm-svn: 122404
 2010-12-22 16:03:00 +00:00
Daniel Dunbar
17e19b2d45 MC/Mach-O/ARM: Stub out RecordARMRelocation, which is mostly a copy of 
RecordRelocation with lots of FIXMEs.

llvm-svn: 122402
 2010-12-22 13:50:05 +00:00
Daniel Dunbar
8db4843cd3 Simplify. 
llvm-svn: 122401
 2010-12-22 13:49:56 +00:00
Daniel Dunbar
bc2bf96e91 MC/Mach-O: Split out RecordARMRelocation for now, it is weird enough it isn't 
clear how to keep in the generic path (yet).
 - Will revisit when it actually works.

llvm-svn: 122400
 2010-12-22 13:49:43 +00:00
Duncan Sands
922251757b Add a generic expansion transform: A op (B op' C) -> (A op B) op' (A op C) 
if both A op B and A op C simplify.  This fires fairly often but doesn't
make that much difference.  On gcc-as-one-file it removes two "and"s and
turns one branch into a select.

llvm-svn: 122399
 2010-12-22 13:36:08 +00:00
Che-Liang Chiou
e73ad4387e ptx: add ld instruction and test 
llvm-svn: 122398
 2010-12-22 10:38:51 +00:00
Duncan Sands
9b28a173fe Add some statistics, good for understanding how much more powerful 
instcombine is compared to instsimplify.

llvm-svn: 122397
 2010-12-22 09:40:51 +00:00
Oscar Fuentes
898b75ee39 Fixes file extension for loadable modules on OS X. 
Patch by Wesley Peck!

llvm-svn: 122395
 2010-12-22 08:30:17 +00:00
Chris Lattner
04ef853e23 Fix a bug in ReduceLoadWidth that wasn't handling extending 
loads properly.  We miscompiled the testcase into:

_test:                                  ## @test
	movl	$128, (%rdi)
	movzbl	1(%rdi), %eax
	ret

Now we get a proper:

_test:                                  ## @test
	movl	$128, (%rdi)
	movsbl	(%rdi), %eax
	movzbl	%ah, %eax
	ret

This fixes PR8757.

llvm-svn: 122392
 2010-12-22 08:02:57 +00:00
Chris Lattner
35fcc63498 more cleanups, move a check for "roundedness" earlier to reject 
unhanded cases faster and simplify code.

llvm-svn: 122391
 2010-12-22 08:01:44 +00:00
Chris Lattner
60dcb2b5c2 reduce indentation and improve comments, no functionality change. 
llvm-svn: 122389
 2010-12-22 07:36:50 +00:00
Wesley Peck
2759b7bc98 Don't generate carry bit when loading immediate values on the Microblaze. 
llvm-svn: 122385
 2010-12-22 01:29:32 +00:00
Wesley Peck
0d64db9772 Add support for some of the LLVM atomic operations to the MBlaze backend. 
llvm-svn: 122384
 2010-12-22 01:15:01 +00:00
Wesley Peck
32c95e5ef4 Modeling the carry bit in the MSR register of the MicroBlaze. 
llvm-svn: 122381
 2010-12-22 00:53:07 +00:00
Wesley Peck
fc577ca406 Fix a regression introduced into the MBlaze delay slot filler. 
llvm-svn: 122379
 2010-12-22 00:22:59 +00:00
Owen Anderson
b4f1511864 Give GVN back the ability to perform simple conditional propagation on conditional branch values. 
I still think that LVI should be handling this, but that capability is some ways off in the future,
and this matters for some significant benchmarks.

llvm-svn: 122378
 2010-12-21 23:54:34 +00:00
Matt Beaumont-Gay
b03146b50a GCC objects to the two sides of a conditional expression having different enum 
types, but they're just getting converted to unsigned anyway, so cast first
(and ask questions later).

llvm-svn: 122377
 2010-12-21 23:43:23 +00:00
Owen Anderson
1ee218de0e Remove dead code. 
llvm-svn: 122371
 2010-12-21 22:31:24 +00:00
Andrew Trick
afec190a28 In DelayForLiveRegsBottomUp, handle instructions that read and write 
the same physical register. Simplifies the fix from the previous
checkin r122211.

llvm-svn: 122370
 2010-12-21 22:27:44 +00:00
Andrew Trick
1e3ad9f721 whitespace 
llvm-svn: 122368
 2010-12-21 22:25:04 +00:00
Dale Johannesen
e0fb87c3d7 Reapply 122353-122355 with fixes. 122354 was wrong; 
the shift type was needed one place, the shift count
type another.  The transform in 123555 had the same
problem.

llvm-svn: 122366
 2010-12-21 21:55:50 +00:00
Benjamin Kramer
369872edfc Add some x86 specific dagcombines for conditional increments. 
(add Y, (sete  X, 0)) -> cmp X, 1; adc  0, Y
(add Y, (setne X, 0)) -> cmp X, 1; sbb -1, Y
(sub (sete  X, 0), Y) -> cmp X, 1; sbb  0, Y
(sub (setne X, 0), Y) -> cmp X, 1; adc -1, Y

for
  unsigned foo(unsigned a, unsigned b) {
    if (a == 0) b++;
    return b;
  }
we now get:
  foo:
    cmpl  $1, %edi
    movl  %esi, %eax
    adcl  $0, %eax
    ret
instead of:
  foo:
    testl %edi, %edi
    sete  %al
    movzbl  %al, %eax
    addl  %esi, %eax
    ret

llvm-svn: 122364
 2010-12-21 21:41:44 +00:00
Benjamin Kramer
fd119319ea GVN's Expression is not POD-like (it contains a SmallVector). Simplify code while at it. 
llvm-svn: 122362
 2010-12-21 21:30:19 +00:00
Dale Johannesen
972aba543a Revert 122353-122355 for the moment, they broke stuff. 
llvm-svn: 122360
 2010-12-21 21:22:27 +00:00
Rafael Espindola
a1091c31ba Simplify EvaluateAsAbsolute now that EvaluateAsRelocatableImpl does all 
the folding it can.

llvm-svn: 122359
 2010-12-21 20:51:42 +00:00
Rafael Espindola
3d9afa3c44 Don't relax org or align. They change size as the relaxation happens, but they 
are not actually relaxed. For example, a section with only alignments will never
needs relaxation.

llvm-svn: 122356
 2010-12-21 20:35:18 +00:00