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8838 Commits

Author SHA1 Message Date
Ted Kremenek
b7236d215b Fix capitalization in #include of FastISel.h. This unbreaks the build on case-sensitive filesystems. 
llvm-svn: 55687
 2008-09-03 02:54:11 +00:00
Evan Cheng
4cef3f6ce1 Unbreak fast isel. 
llvm-svn: 55685
 2008-09-03 01:04:47 +00:00
Evan Cheng
43c7084625 Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class. 
llvm-svn: 55679
 2008-09-03 00:03:49 +00:00
Dale Johannesen
46f19abcec Fix some bugs in the code sequences for atomics. 
llvm-svn: 55643
 2008-09-02 20:30:23 +00:00
Evan Cheng
126bd60288 Add Mac OS X compatible JIT callback routine. 
llvm-svn: 55625
 2008-09-02 07:49:03 +00:00
Evan Cheng
e97c48a34a Revamp ARM JIT. 
llvm-svn: 55624
 2008-09-02 06:52:38 +00:00
Evan Cheng
9817be2f96 Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes. 
llvm-svn: 55623
 2008-09-02 06:51:36 +00:00
Evan Cheng
738426a2a1 Control flow instruction encodings. 
llvm-svn: 55601
 2008-09-01 08:25:56 +00:00
Evan Cheng
36170e63a3 ldm / stm instruction encodings. 
llvm-svn: 55599
 2008-09-01 07:48:18 +00:00
Evan Cheng
01019d7909 AXI2 and AXI3 instruction encodings. 
llvm-svn: 55598
 2008-09-01 07:34:13 +00:00
Evan Cheng
fdae49e627 Reorganize instruction formats again; AXI1 encoding. 
llvm-svn: 55597
 2008-09-01 07:19:00 +00:00
Evan Cheng
26305b192f addrmode3 instruction encodings. 
llvm-svn: 55596
 2008-09-01 07:00:14 +00:00
Evan Cheng
eb40cb3e42 Reorganize some instruction format definitions. No functionality change. 
llvm-svn: 55594
 2008-09-01 01:51:14 +00:00
Evan Cheng
fa095aec1e Rest of addrmode2 instruction encodings. 
llvm-svn: 55593
 2008-09-01 01:27:33 +00:00
Evan Cheng
4c8338c0d3 Addr2 word / byte load encodings. 
llvm-svn: 55591
 2008-08-31 19:02:21 +00:00
Evan Cheng
94f3d276c6 Addr1 instructions opcodes are encoded in bits 21-24; encode S bit. 
llvm-svn: 55590
 2008-08-31 18:32:16 +00:00
Gabor Greif
7db742d8c2 fix a bunch of 80-col violations 
llvm-svn: 55588
 2008-08-31 15:37:04 +00:00
Bill Wendling
297eb080b6 Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR 
instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.

llvm-svn: 55582
 2008-08-31 02:59:23 +00:00
Bill Wendling
8faa2f3ec4 Expand for ROTR with MVT::i64. 
Dale, Could you please review this?

llvm-svn: 55581
 2008-08-31 02:53:19 +00:00
Gabor Greif
8fa04b6eb0 fix some 80-col violations 
llvm-svn: 55565
 2008-08-30 10:09:02 +00:00
Evan Cheng
c3c439a624 For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these. 
llvm-svn: 55562
 2008-08-30 08:54:22 +00:00
Evan Cheng
4bc8c9652e Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). 
llvm-svn: 55558
 2008-08-30 02:03:58 +00:00
Dale Johannesen
1cfbb25e75 Add ppc partial-word ATOMIC_CMP_SWAP. 
llvm-svn: 55554
 2008-08-30 00:08:53 +00:00
Evan Cheng
c1c53221c5 Swap fp comparison operands and change predicate to allow load folding (safely this time). 
llvm-svn: 55553
 2008-08-29 23:22:12 +00:00
Evan Cheng
a884330e08 Use static_cast instead of C style cast. 
llvm-svn: 55552
 2008-08-29 23:21:31 +00:00
Evan Cheng
17382f9ffb Backing out 55521. Not safe. 
llvm-svn: 55548
 2008-08-29 22:13:21 +00:00
Dale Johannesen
bc977ce106 Add partial word version of ATOMIC_SWAP. 
llvm-svn: 55546
 2008-08-29 18:29:46 +00:00
Owen Anderson
3aa3841da2 Add initial support for fast isel of instructions that have inputs pinned to physical registers. 
llvm-svn: 55545
 2008-08-29 17:45:56 +00:00
Evan Cheng
3fb02ae0b6 TableGen'ing instruction encodings. 
llvm-svn: 55533
 2008-08-29 07:42:03 +00:00
Evan Cheng
b38decd917 addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode. 
llvm-svn: 55531
 2008-08-29 07:40:52 +00:00
Evan Cheng
5150e3da45 MVN is addrmode1. 
llvm-svn: 55530
 2008-08-29 07:36:24 +00:00
Evan Cheng
f90bc9a050 More refactoring. 
llvm-svn: 55528
 2008-08-29 06:41:12 +00:00
Evan Cheng
cdd06ba3f4 Swap fp comparison operands and change predicate to allow load folding. 
llvm-svn: 55521
 2008-08-28 23:48:31 +00:00
Evan Cheng
c50df85672 Refactor ARM instruction format definitions into a separate file. No functionality changes. 
llvm-svn: 55518
 2008-08-28 23:39:26 +00:00
Dan Gohman
c7b8401b77 Add a target callback for FastISel. 
llvm-svn: 55512
 2008-08-28 23:21:34 +00:00
Gabor Greif
5ec5f19852 remove tabs, fix > 80 cols 
llvm-svn: 55511
 2008-08-28 23:19:51 +00:00
Gabor Greif
86c795a8ca erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics 
llvm-svn: 55504
 2008-08-28 21:40:38 +00:00
Mon P Wang
7566974359 In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN 
llvm-svn: 55499
 2008-08-28 21:04:05 +00:00
Rafael Espindola
1cd4fc3111 Use resize instead of reserve. Reserve doesn't change size(). 
llvm-svn: 55486
 2008-08-28 18:32:53 +00:00
Dale Johannesen
e9a1266213 Implement partial-word binary atomics on ppc. 
llvm-svn: 55478
 2008-08-28 17:53:09 +00:00
Evan Cheng
419506a149 FsFLD0S{S|D} and V_SETALLONES are as cheap as moves. 
llvm-svn: 55466
 2008-08-28 07:52:25 +00:00
Dale Johannesen
490c016734 Split the ATOMIC NodeType's to include the size, e.g. 
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.

llvm-svn: 55457
 2008-08-28 02:44:49 +00:00
Bill Wendling
0b5b31a0be Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the 
SSE2 registers as well as the MMX registers.

llvm-svn: 55436
 2008-08-27 21:32:04 +00:00
Dan Gohman
3976cccecd Reinstate the x86-64 portion of r55190. When doing extloads into 
64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.

llvm-svn: 55422
 2008-08-27 17:33:15 +00:00
Gabor Greif
4b86114f92 disallow direct access to SDValue::ResNo, provide a getter instead 
llvm-svn: 55394
 2008-08-26 22:36:50 +00:00
Owen Anderson
fc7b8f3073 These assertions should be return false's instead, allowing the client to detect the failure. 
llvm-svn: 55377
 2008-08-26 18:50:40 +00:00
Owen Anderson
5fef19facf Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested 
was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.

llvm-svn: 55375
 2008-08-26 18:03:31 +00:00
Chris Lattner
c5c00890e5 If an xmm register is referenced explicitly in an inline asm, make sure to 
assign it to a version of the xmm register with the regclass that matches its
type.  This fixes PR2715, a bug handling some crazy xpcom case in mozilla.

llvm-svn: 55358
 2008-08-26 06:19:02 +00:00
Evan Cheng
65d29b2553 This is done. 
llvm-svn: 55348
 2008-08-26 01:13:44 +00:00
Dale Johannesen
f201a3aaf3 Implement 32 & 64 bit versions of PPC atomic 
binary primitives.

llvm-svn: 55343
 2008-08-25 22:34:37 +00:00