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Commit Graph

131479 Commits

Author SHA1 Message Date
Simon Pilgrim
f9df31c43a [X86][AVX512] Added another masked shuffle combine from load test
llvm-svn: 269077
2016-05-10 16:55:20 +00:00
Krzysztof Parzyszek
94dfb264c1 [ScheduleDAG] Make sure to process all def operands before any use operands
An example from Hexagon where things went wrong:
  %R0<def> = L2_loadrigp <ga:@fp04>      ; load function address
  J2_callr %R0<kill>, ..., %R0<imp-def>  ; call *R0, return value in R0

ScheduleDAGInstrs::buildSchedGraph would visit all instructions going
backwards, and in each instruction it would visit all operands in their
order on the operand list. In the case of this call, it visited the use
of R0 first, then removed it from the set Uses after it visited the def.
This caused the DAG to be missing the data dependence edge on R0 between
the load and the call.

Differential Revision: http://reviews.llvm.org/D20102

llvm-svn: 269076
2016-05-10 16:50:30 +00:00
Marcin Koscielnicki
0b542252f9 [PR27599] [SystemZ] [SelectionDAG] Fix extension of atomic cmpxchg result.
Currently, SelectionDAG assumes 8/16-bit cmpxchg returns either a sign
extended result, or a zero extended result.  SystemZ takes a third
option by returning junk in the high bits (rotated contents of the other
bytes in the memory word).  In that case, don't use Assert*ext, and
zero-extend the result ourselves if a comparison is needed.

Differential Revision: http://reviews.llvm.org/D19800

llvm-svn: 269075
2016-05-10 16:49:04 +00:00
Nadav Rotem
9adba64398 Update my email address.
llvm-svn: 269073
2016-05-10 16:23:54 +00:00
Simon Pilgrim
0a2ddfd584 [X86][AVX] Added some shuffle combine from load tests
As discussed on D19198 - we need to check what happens when we shuffle with different value type to the load

llvm-svn: 269068
2016-05-10 16:08:24 +00:00
Teresa Johnson
e31605427f [ThinLTO] Add option to emit imports files for distributed backends
Summary:
Add support for emission of plaintext lists of the imported files for
each distributed backend compilation. Used for distributed build file
staging.

Invoked with new gold-plugin thinlto-emit-imports-files option, which is
only valid with thinlto-index-only (i.e. for distributed builds), or
from llvm-lto with new -thinlto-action=emitimports value.

Depends on D19556.

Reviewers: joker.eph

Subscribers: llvm-commits, joker.eph

Differential Revision: http://reviews.llvm.org/D19636

llvm-svn: 269067
2016-05-10 15:54:09 +00:00
Renato Golin
2d3223210a [docs] Fix unexpected indentation in HowToCrossCompileLLVM.rst
Seems like my sphynx version is different than the one in the bot, as it
accepted everything locally. I think this is the right fix...

llvm-svn: 269062
2016-05-10 14:02:46 +00:00
Teresa Johnson
4147326797 Restore "[ThinLTO] Emit individual index files for distributed backends"
This restores commit r268627:
    Summary:
    When launching ThinLTO backends in a distributed build (currently
    supported in gold via the thinlto-index-only plugin option), emit
    an individual index file for each backend process as described here:
    http://lists.llvm.org/pipermail/llvm-dev/2016-April/098272.html

    ...

    Differential Revision: http://reviews.llvm.org/D19556

Address msan failures by avoiding std::prev on map.end(), the
theory is that this is causing issues due to some known UB problems
in __tree.

llvm-svn: 269059
2016-05-10 13:48:23 +00:00
Renato Golin
61778268f4 [docs] Change CrossCompilation guidde to reflect changes in Clang/GCC
HowToCrossCompile was outdated and generating too much traffic on the mailing
list with similar queries. This change helps offset most of the problems that
were reported recently including:

 * Removing the -ccc-gcc-name, adding --sysroot
 * Making references to Debian's multiarch for target libraries
 * Expanding -DCMAKE_CXX_FLAGS for both GCC and Clang
 * Some formatting and clarifications in the text

llvm-svn: 269054
2016-05-10 12:54:12 +00:00
Silviu Baranga
2646a05589 [LAA] Use re-written SCEV expressions when computing distances
This removes a redundant stride versioning step (we already
do it in getPtrStride, so it has no effect) and uses PSE to
get the SCEV expressions for the source and destination
(this might have changed when getPtrStride was called).

I discovered this through code inspection, and couldn't
produce a regression test for it.

llvm-svn: 269052
2016-05-10 12:28:49 +00:00
James Molloy
0bbc10508e Revert "[VectorUtils] Query number of sign bits to allow more truncations"
This was a fairly simple patch but on closer inspection was seriously flawed and caused PR27690.

This reverts commit r268921.

llvm-svn: 269051
2016-05-10 12:27:23 +00:00
Daniel Sanders
0c5254b797 [mips][ias] Make the default path unreachable in needsRelocateWithSymbol() (except for N64).
Following post-commit comments on r268900 from Rafael Espindola:
The missing relocations are now explicitly listed in the switch statement with
appropriate FIXME comments and the default path is now unreachable. The
temporary exception to this is that compound relocations for N64 still have a
default path that returns true. This is because fixing that case ought to be a
separate patch.

Also make R_MIPS_NONE return false since it has no effect on the section data.

llvm-svn: 269047
2016-05-10 12:17:04 +00:00
Jeroen Ketema
62b073095f [OCaml] Update core test and re-enable testing
Differential Revision: http://reviews.llvm.org/D19828

llvm-svn: 269040
2016-05-10 11:19:20 +00:00
Simon Pilgrim
ea0f8c3cc2 [X86][AVX512] Added masked version of MOVDDUP test with 16f32
llvm-svn: 269038
2016-05-10 10:30:00 +00:00
Chuang-Yu Cheng
79a3fbfded Update Debug Intrinsics in RewriteUsesOfClonedInstructions in LoopRotation
Loop rotation clones instruction from the old header into the preheader. If
there were uses of values produced by these instructions that were outside
the loop, we have to insert PHI nodes to merge the two values. If the values
are used by DbgIntrinsics they will be used as a MetadataAsValue of a
ValueAsMetadata of the original values, and iterating all of the uses of the
original value will not update the DbgIntrinsics. The new code checks if the
values are used by DbgIntrinsics and if so, updates them using essentially
the same logic as the original code.

The attached testcase demonstrates the issue. Without the fix, the
DbgIntrinic outside the loop uses values computed inside the loop, even
though these values do not dominate the DbgIntrinsic.

Author: Thomas Jablin (tjablin)
Reviewers: dblaikie aprantl kbarton hfinkel cycheng

http://reviews.llvm.org/D19564

llvm-svn: 269034
2016-05-10 09:45:44 +00:00
Arnaud A. de Grandmaison
6c99fa9cb1 [InstCombine] Remove trivially empty va_start/va_end and va_copy/va_end ranges.
When a va_start or va_copy is immediately followed by a va_end (ignoring
debug information or other start/end in between), then it is safe to
remove the pair. As this code shares some commonalities with the lifetime
markers, this has been factored to helper functions.

This InstCombine pattern kicks-in 3 times when running the LLVM test
suite.

llvm-svn: 269033
2016-05-10 09:24:49 +00:00
Chris Dewhurst
176f760d09 [Sparc][LEON] Itineraries unit test.
Added test to check LeonItineraries are being applied by code checked-in two weeks ago in r267121.

Phabricator Review: http://reviews.llvm.org/D19359

llvm-svn: 269032
2016-05-10 09:09:20 +00:00
Daniel Sanders
ccc207e225 Clarify the difference between ISD::BITCAST and the bitcast instruction from LLVM-IR.
Subscribers: llvm-commits, hfinkel

Differential Revision: http://reviews.llvm.org/D16464

llvm-svn: 269031
2016-05-10 09:01:54 +00:00
Renato Golin
477f18731f Revert "[PGO] Fix __llvm_profile_raw_version linkage in MACHO IR instrumentation generates a COMDAT symbol __llvm_profile_raw_version to overwrite the same symbol in profile run-time to distinguish IR profiles from Clang generated profiles. In MACHO, LinkOnceODR linkage is used due to the lack of COMDAT support."
This reverts commits r268969, r268979 and r268984. They had target specific test
in generic directories without the correct specifiers and made it hard for us to
come up with a good solution by rapidly committing untested changes.

This test needs to be in a target specific directory or have the correct REQUIRED
identifier.

llvm-svn: 269027
2016-05-10 08:23:57 +00:00
Jonas Paulsson
54b5410b72 [foldMemoryOperand()] Pass LiveIntervals to enable liveness check.
SystemZ (and probably other targets as well) can fold a memory operand
by changing the opcode into a new instruction that as a side-effect
also clobbers the CC-reg.

In order to do this, liveness of that reg must first be checked. When
LIS is passed, getRegUnit() can be called on it and the right
LiveRange is computed on demand.

Reviewed by Matthias Braun.
http://reviews.llvm.org/D19861

llvm-svn: 269026
2016-05-10 08:09:37 +00:00
Elena Demikhovsky
7866776645 [LoopVectorize] Handling induction variable with non-constant step.
Allow vectorization when the step is a loop-invariant variable.
This is the loop example that is getting vectorized after the patch:

 int int_inc;
 int bar(int init, int *restrict A, int N) {

  int x = init;
  for (int i=0;i<N;i++){
    A[i] = x;
    x += int_inc;
  }
  return x;
 }

"x" is an induction variable with *loop-invariant* step.
But it is not a primary induction. Primary induction variable with non-constant step is not handled yet.

Differential Revision: http://reviews.llvm.org/D19258

llvm-svn: 269023
2016-05-10 07:33:35 +00:00
Denis Zobnin
9ca47eba01 [LAA] Rename "isStridedPtr" with "getPtrStride". NFC.
Changing misleading function name was approved in http://reviews.llvm.org/D17268.
Patch by Roman Shirokiy.

llvm-svn: 269021
2016-05-10 05:55:16 +00:00
Matthias Braun
7f83dd0cd2 liveness.mir requires asserts to use -debug-only
llvm-svn: 269020
2016-05-10 05:38:47 +00:00
Craig Topper
1904f2268b [X86][AVX512] Strengthen the assertions from r269001. We need VLX to use the 128/256-bit move opcodes for extended registers.
llvm-svn: 269019
2016-05-10 05:28:04 +00:00
Craig Topper
601759c5c1 [X86] Add ZMM registers to the X86_INTR calling convention preserved mask when AVX512 is enabled.
llvm-svn: 269018
2016-05-10 05:28:02 +00:00
Craig Topper
aa2acf8da0 [X86] Update X86_INTR calling convention to save ZMM registers instead of YMM registers when AVX512 is enabled.
llvm-svn: 269017
2016-05-10 05:27:56 +00:00
Matthias Braun
0e4167d266 LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()
We now use LiveRangeCalc::extendToUses() instead of a specially designed
algorithm in constructMainRangeFromSubranges():
- The original motivation for constructMainRangeFromSubranges() were
  differences between the main liverange and subranges because of hidden
  dead definitions. This case however cannot happen anymore with the
  DetectDeadLaneMasks pass in place.
- It simplifies the code.
- This fixes a longstanding bug where we did not properly create new SSA
  values on merging control flow (the MachineVerifier missed most of
  these cases).
- Move constructMainRangeFromSubranges() to LiveIntervalAnalysis and
  LiveRangeCalc to better match the implementation/available helper
  functions.

llvm-svn: 269016
2016-05-10 04:51:14 +00:00
Matthias Braun
7b8ba8114b LiveInterval: Avoid unnecessary auto, add const; NFC
llvm-svn: 269015
2016-05-10 04:51:09 +00:00
Matthias Braun
93cd817344 llc: Print+Verify machine function after loading it
In -run-pass mode verify/print machine function immediately after
loading the .mir file if -verify-machineinstr/-print-machineinstrs
option is specified.

llvm-svn: 269014
2016-05-10 04:51:07 +00:00
Matthias Braun
298c8c892c TargetPassConfig: Set PrintMachineCode even if addMachinePasses() does not run.
llvm-svn: 269013
2016-05-10 04:51:04 +00:00
Dan Gohman
13d15dbc40 [WebAssembly] Move register stackification and coloring to a late phase.
Move the register stackification and coloring passes to run very late, after
PEI, tail duplication, and most other passes. This means that all code emitted
and expanded by those passes is now exposed to these passes. This also
eliminates the need for prologue/epilogue code to be manually stackified,
which significantly simplifies the code.

This does require running LiveIntervals a second time. It's useful to think
of these late passes not as late optimization passes, but as a domain-specific
compression algorithm based on knowledge of liveness information. It's used to
compress the code after all conventional optimizations are complete, which is
why it uses LiveIntervals at a phase when actual optimization passes don't
typically need it.

Differential Revision: http://reviews.llvm.org/D20075

llvm-svn: 269012
2016-05-10 04:24:02 +00:00
Matthias Braun
556abb392a CodeGen: Move TargetPassConfig from Passes.h to an own header; NFC
Many files include Passes.h but only a fraction needs to know about the
TargetPassConfig class. Move it into an own header. Also rename
Passes.cpp to TargetPassConfig.cpp while we are at it.

llvm-svn: 269011
2016-05-10 03:21:59 +00:00
Matthias Braun
0fdab91763 PrologEpilogInserter: Remove unnecessary dependency
llvm-svn: 269010
2016-05-10 03:21:47 +00:00
Matthias Braun
70befc4204 Appease MSVC
Apply a similar fix to the one in r269006 to LiveIntervalTest.cpp.

llvm-svn: 269009
2016-05-10 03:03:55 +00:00
Sanjoy Das
bbb7dedca9 [ValueTracking] Use guards to prove non-nullness of a value
Reviewers: apilipenko, majnemer, reames

Subscribers: mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D20044

llvm-svn: 269008
2016-05-10 02:35:44 +00:00
Sanjoy Das
cf2951e884 [BasicAA] Guard intrinsics don't write to memory
Summary:
The idea is very close to what we do for assume intrinsics: we mark the
guard intrinsics as writing to arbitrary memory to maintain control
dependence, but under the covers we teach AA that they do not mod any
particular memory location.

Reviewers: chandlerc, hfinkel, gbiv, reames

Subscribers: george.burgess.iv, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D19575

llvm-svn: 269007
2016-05-10 02:35:41 +00:00
Matthias Braun
4a59843466 Try to appease clang-x64-ninja-win7 bot.
Looks like you need the complete definition of "X" when calling a "X
&func()" declared function even when not using the result further.

llvm-svn: 269006
2016-05-10 02:09:32 +00:00
Matthias Braun
8ad583e459 llc: Rework -run-pass option
We now construct a custom pass pipeline instead of injecting
start-before/stop-after into the default pipeline construction. This
allows to specify any pass known to the pass registry. Previously
specifying indirectly added analysis passes or passes not added to the
pipeline add all would not be added and we would silently do nothing.

This also restricts the -run-pass option to cases with .mir input.

llvm-svn: 269003
2016-05-10 01:32:44 +00:00
Matthias Braun
f2237dd6c8 LLVMTargetMachine: Add functions to create MIModuleInfo/MIFunction; NFC
Add convenience function to create MachineModuleInfo and
MachineFunctionAnalysis passes and add them to a pass manager.

Despite factoring out some shared code in
LiveIntervalTest/LLVMTargetMachine this will be used by my upcoming llc
change.

llvm-svn: 269002
2016-05-10 01:32:40 +00:00
Quentin Colombet
4c5a2694f9 [X86][AVX512] Use the proper load/store for AVX512 registers.
When loading or storing AVX512 registers we were not using the AVX512
variant of the load and store for VR128 and VR256 like registers.
Thus, we ended up with the wrong encoding and actually were dropping the
high bits of the instruction. The result was that we load or store the
wrong register. The effect is visible only when we emit the object file
directly and disassemble it. Then, the output of the disassembler does
not match the assembly input.

This is related to llvm.org/PR27481.

llvm-svn: 269001
2016-05-10 01:09:14 +00:00
Evgeniy Stepanov
aba7343f5c Don't inline functions with different SafeStack attributes.
llvm-svn: 268999
2016-05-10 00:33:07 +00:00
Sanjoy Das
ed0c9c71c4 [SCEVExpander] Clang format expressions; NFC
The boolean expressions are somewhat hard to read otherwise.

llvm-svn: 268998
2016-05-10 00:32:31 +00:00
Sanjoy Das
5e39b474b8 [SCEV] Use guards to prove predicates
We can use calls to @llvm.experimental.guard to prove predicates,
relying on the fact that in all locations domianted by a call to
@llvm.experimental.guard the predicate it is guarding is known to be
true.

llvm-svn: 268997
2016-05-10 00:31:49 +00:00
Justin Lebar
d48c5d506c [nvvm] Mark ldu and ldg intrinsics as IntrArgMemOnly.
Summary:
Previously these intrinsics were marked as can-read any memory address.
Now they're marked as reading only the pointer they're passed.

Reviewers: rnk

Subscribers: jholewinski, llvm-commits, tra

Differential Revision: http://reviews.llvm.org/D20080

llvm-svn: 268996
2016-05-10 00:31:25 +00:00
Justin Lebar
e84867be95 Minor formatting fixes in LoopUnroll.cpp.
llvm-svn: 268995
2016-05-10 00:31:23 +00:00
Justin Lebar
e9c3e87ae5 [NVPTX] Change begin/end inline asm comments to "begin/end inline asm".
Previously it was just "// inline asm", which made it tricky to read
code with lots of inline assembly.

llvm-svn: 268994
2016-05-10 00:31:22 +00:00
Justin Lebar
8223b14a5b [NVVM] Add comments to NVVM intrinsics listing.
llvm-svn: 268993
2016-05-10 00:31:20 +00:00
Derek Schuff
15d6ef9c78 [WebAssembly] Disable 128-bit shift libcalls
Currently the signature of the functions
i128(i128, i32) aka void(i32, i64, i64, i32) doesn't match the signature
of the call emitted by the default lowering, void(i32, i64, i64).

llvm-svn: 268991
2016-05-10 00:14:07 +00:00
Justin Bogner
2067192e3a SDAG: Stop relying on Select's return value in SystemZ's splitLargeImmediate. NFC
The call to Select on Upper here happens in an unusual order in order
to defeat the constant folding that getNode() does. Add a comment
explaining why we can't just move the Select to later to avoid a
Handle, and wrap the call to SelectCode in a handle so we don't need
its return value.

This is part of the work to have Select return void instead of an
SDNode *, which is in turn part of llvm.org/pr26808.

llvm-svn: 268990
2016-05-09 23:54:23 +00:00
Eugene Zelenko
509e9c3f2e Fix some Clang-tidy modernize-deprecated-headers and Include What You Use warnings; other minor fixes.
Differential revision: http://reviews.llvm.org/D20042

llvm-svn: 268989
2016-05-09 23:11:38 +00:00