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109 Commits

Author SHA1 Message Date
Vincent Lejeune
2f252fdf26 R600: Anti dep better handled in tex clause 
llvm-svn: 183592
 2013-06-07 23:30:26 +00:00
Tom Stellard
7c091ffbf7 R600: Fix calculation of stack offset in AMDGPUFrameLowering 
We weren't computing structure size correctly and we were relying on
the original alloca instruction to compute the offset, which isn't
always reliable.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183568
 2013-06-07 20:52:05 +00:00
Tom Stellard
f4646ab025 R600: Fix the fetch limits for R600 generation GPUs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64257

llvm-svn: 183560
 2013-06-07 20:28:55 +00:00
Vincent Lejeune
dd2a468cbd R600: Add a pass that merge Vector Register 
Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

llvm-svn: 183343
 2013-06-05 21:38:04 +00:00
Vincent Lejeune
cc7d08e974 R600: Schedule copy from phys register at beginning of block 
It allows regalloc pass to remove them by trivially assigning associated reg

llvm-svn: 183336
 2013-06-05 20:27:35 +00:00
Tom Stellard
ecf6bd2eaa R600: Make sure to schedule AR register uses and defs in the same clause 
Reviewed-by: vljn at ovi.com
llvm-svn: 183294
 2013-06-05 03:43:06 +00:00
Rafael Espindola
f5e919b2e6 Revert "R600: Add a pass that merge Vector Register" 
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.

llvm-svn: 183286
 2013-06-05 01:48:30 +00:00
Vincent Lejeune
57d56af481 R600: Add a pass that merge Vector Register 
llvm-svn: 183279
 2013-06-04 23:17:26 +00:00
Vincent Lejeune
7c89765008 R600: Const/Neg/Abs can be folded to dot4 
llvm-svn: 183278
 2013-06-04 23:17:15 +00:00
Vincent Lejeune
8d2ef79cb9 R600: Swizzle texture/export instructions 
llvm-svn: 183229
 2013-06-04 15:04:53 +00:00
Vincent Lejeune
e7cc832b43 R600: Add a test for r183108 
llvm-svn: 183228
 2013-06-04 15:03:35 +00:00
Tom Stellard
0c2bbb2a1f R600/SI: Add support for work item and work group intrinsics 
llvm-svn: 183138
 2013-06-03 17:40:18 +00:00
Tom Stellard
0faf53682e R600/SI: Add a calling convention for compute shaders 
llvm-svn: 183137
 2013-06-03 17:40:11 +00:00
Tom Stellard
47a52f3e69 R600/SI: Custom lower i64 sign_extend 
llvm-svn: 183136
 2013-06-03 17:40:03 +00:00
Tom Stellard
7e44e13b15 R600/SI: Add support for global loads 
llvm-svn: 183131
 2013-06-03 17:39:43 +00:00
Vincent Lejeune
55871f8f8a R600: use capital letter for PV channel 
llvm-svn: 183107
 2013-06-03 15:44:35 +00:00
Tom Stellard
dee18e3abb R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg 
Patch by: Vincent Lejeune

https://bugs.freedesktop.org/show_bug.cgi?id=64877

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 182600
 2013-05-23 18:26:42 +00:00
Tom Stellard
6cdacd1792 R600: Fix rotr.ll on non-asserts builds 
The -debug-only option is only available on asserts builds.

llvm-svn: 182291
 2013-05-20 15:28:48 +00:00
Tom Stellard
d72698331e R600/SI: Add pattern for rotr 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182286
 2013-05-20 15:02:24 +00:00
Tom Stellard
5ca265d214 R600: Swap the legality of rotl and rotr 
The hardware supports rotr and not rotl.

llvm-svn: 182285
 2013-05-20 15:02:19 +00:00
Tom Stellard
1609774b15 R600/SI: Add patterns for 64-bit shift operations 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182284
 2013-05-20 15:02:12 +00:00
Vincent Lejeune
c8aad4509a R600: Lower int_load_input to copyFromReg instead of Register node 
It solves a bug uncovered by dot4 patch where the register class of
int_load_input use was ignored.

llvm-svn: 182130
 2013-05-17 16:51:06 +00:00
Vincent Lejeune
5a2e018ab6 R600: Use bottom up scheduling algorithm 
llvm-svn: 182129
 2013-05-17 16:50:56 +00:00
Vincent Lejeune
2bf65b1826 R600: Use depth first scheduling algorithm 
It should increase PV substitution opportunities and lower gpr
usage (pending computations path are "flushed" sooner)

llvm-svn: 182128
 2013-05-17 16:50:44 +00:00
Vincent Lejeune
152473c61c R600: Relax some vector constraints on Dot4. 
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.

llvm-svn: 182126
 2013-05-17 16:50:32 +00:00
Vincent Lejeune
0c663b698a R600: Improve texture handling 
llvm-svn: 182125
 2013-05-17 16:50:20 +00:00
Vincent Lejeune
b57cb76b6d R600: Rename 128 bit registers. 
Almost all instructions that takes a 128 bits reg as input (fetch, export...)
have the abilities to swizzle their argument and output. Instead of printing
default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions
print potentially optimized swizzles themselves.

llvm-svn: 182124
 2013-05-17 16:50:09 +00:00
Tom Stellard
a4cc081e08 R600: Fix encoding for R600 family GPUs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64193
https://bugs.freedesktop.org/show_bug.cgi?id=64257
https://bugs.freedesktop.org/show_bug.cgi?id=64320

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 182113
 2013-05-17 15:23:21 +00:00
Michel Danzer
451c4b7507 R600/SI: Add lit test coverage for the remaining patterns added recently 
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 181775
 2013-05-14 09:53:30 +00:00
Tom Stellard
7edf38bf1f R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns 
The BFE optimization was the only one we were actually using, and it was
emitting an intrinsic that we don't support.

https://bugs.freedesktop.org/show_bug.cgi?id=64201

Reviewed-by: Christian König <christian.koenig@amd.com>

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181580
 2013-05-10 02:09:45 +00:00
Tom Stellard
ed363c57b2 R600: Expand SUB for v2i32/v4i32 
Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181579
 2013-05-10 02:09:39 +00:00
Tom Stellard
3ca3d250c6 R600: Expand MUL for v4i32/v2i32 
Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181578
 2013-05-10 02:09:34 +00:00
Tom Stellard
56fef8261c R600: Expand SRA for v4i32/v2i32 
v2: Add v4i32 test

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181577
 2013-05-10 02:09:29 +00:00
Tom Stellard
5d4a5a0d37 R600: Expand vselect for v4i32 and v2i32 
v2: Add vselect v4i32 test

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181576
 2013-05-10 02:09:24 +00:00
Michel Danzer
e95e9672c2 R600/SI: Add lit tests for llvm.SI.imageload and llvm.SI.resinfo intrinsics 
Adapted from the llvm.SI.sample test.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 181425
 2013-05-08 13:07:29 +00:00
Tom Stellard
fb8e73f3af R600: Emit config values in register / value pairs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181228
 2013-05-06 17:50:51 +00:00
Tom Stellard
6c3f6e1b02 R600: Stop emitting the instruction type byte before each instruction 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181225
 2013-05-06 17:50:44 +00:00
Tom Stellard
ebe049fd75 R600: Emit ISA for CALL_FS_* instructions 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181223
 2013-05-06 17:50:26 +00:00
Tom Stellard
2165728987 R600: Expand vector or, shl, srl, and xor nodes 
llvm-svn: 181035
 2013-05-03 17:21:31 +00:00
Tom Stellard
f2fd0109a0 R600: Add pattern for SHA-256 Ma function 
This can be optimized using the BFI_INT instruction.

llvm-svn: 181033
 2013-05-03 17:21:20 +00:00
Vincent Lejeune
5d7b2a4aea R600: Signed literals are 64bits wide 
llvm-svn: 180960
 2013-05-02 21:53:03 +00:00
Vincent Lejeune
3ff31b75b3 R600: If previous bundle is dot4, PV valid chan is always X 
llvm-svn: 180959
 2013-05-02 21:52:55 +00:00
Vincent Lejeune
97fb65a788 R600: Add a test to check that use_kill is emitted 
llvm-svn: 180958
 2013-05-02 21:52:46 +00:00
Vincent Lejeune
62da1453e1 R600: Prettier asmPrint of Alu 
llvm-svn: 180956
 2013-05-02 21:52:30 +00:00
Manman Ren
0b37dd0efc TBAA: remove !tbaa from testing cases if not used. 
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.

llvm-svn: 180796
 2013-04-30 17:52:57 +00:00
Vincent Lejeune
25352bd54f R600: fix loop-address.ll test 
Texture cache is now used when shader type is not specified

llvm-svn: 180785
 2013-04-30 12:47:56 +00:00
Vincent Lejeune
29f24e0ce8 R600: use native for alu 
llvm-svn: 180761
 2013-04-30 00:14:38 +00:00
Vincent Lejeune
e641cd06c9 R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions 
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache

llvm-svn: 180755
 2013-04-30 00:13:39 +00:00
Tom Stellard
33e7a52e1c R600: Use correct CF_END instruction on Northern Island GPUs 
llvm-svn: 180735
 2013-04-29 22:23:58 +00:00
Tom Stellard
a22d2b47f3 R600: Fix encoding of CF_END_{EG, R600} instructions 
The EOP bit was not being encoded.

llvm-svn: 180734
 2013-04-29 22:23:54 +00:00