RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 20:12:56 +02:00
Code Issues Projects Releases Wiki Activity
128,208 Commits 4 Branches 5 Tags 704 MiB
fba583ca7a
Commit Graph

87738 Commits

Author SHA1 Message Date
Chandler Carruth
4def732ecd [LICM] Teach LICM how to handle cases where the alias set tracker was 
merged into a loop that was subsequently unrolled (or otherwise nuked).

In this case it can't merge in the ASTs for any remaining nested loops,
it needs to re-add their instructions dircetly.

The fix is very isolated, but I've pulled the code for merging blocks
into the AST into a single place in the process. The only behavior
change is in the case which would have crashed before.

This fixes a crash reported by Mikael Holmen on the list after r261316
restored much of the loop pass pipelining and allowed us to actually do
this kind of nested transformation sequenc. I've taken that test case
and further reduced it into the somewhat twisty maze of loops in the
included test case. This does in fact trigger the bug even in this
reduced form.

llvm-svn: 262108
 2016-02-27 04:34:07 +00:00
Kostya Serebryany
33b6a19483 [libFuzzer] fixing the bot 
llvm-svn: 262106
 2016-02-27 03:14:23 +00:00
Mike Aizatsky
efd9fa98d1 [sancov] do not instrument nodes that are full pre-dominators 
Summary:
Without tree pruning clang has 2,667,552 points.
Wiht only dominators pruning: 1,515,586.
With both dominators & predominators pruning: 1,340,534.

Differential Revision: http://reviews.llvm.org/D17671

llvm-svn: 262103
 2016-02-27 02:10:27 +00:00
Kostya Serebryany
471f3a8bda [libFuzzer] speedup path coverage handling 
llvm-svn: 262102
 2016-02-27 01:50:16 +00:00
Junmo Park
8063e61895 Minor code cleanup. NFC. 
llvm-svn: 262096
 2016-02-27 01:10:43 +00:00
Reid Kleckner
43aeb743c9 [InstCombine] Be more conservative about removing stackrestore 
We ended up removing a save/restore pair around an inalloca call,
leading to a miscompile in Chromium.

llvm-svn: 262095
 2016-02-27 00:53:54 +00:00
Cong Hou
1cb5dabaaa Fix a bug in isVectorReductionOp() in SelectionDAGBuilder.cpp that may cause assertion failure on AArch64. 
llvm-svn: 262091
 2016-02-26 23:25:30 +00:00
Ahmed Bougacha
f14633274b [X86] Fix a stale comment. NFC. 
llvm-svn: 262087
 2016-02-26 22:59:57 +00:00
Ahmed Bougacha
05e77f2852 [X86] Remove the unused SDTX86atomicBinary. NFC. 
llvm-svn: 262086
 2016-02-26 22:59:41 +00:00
Philip Reames
a3ddb00a03 [LVI] Extend select handling to catch min/max/clamp idioms 
Most of this is fairly straight forward. Add handling for min/max via existing matcher utility and ConstantRange routines.  Add handling for clamp by exploiting condition constraints on inputs.  

Note that I'm only handling two constant ranges at this point. It would be reasonable to consider treating overdefined as a full range if the instruction is typed as an integer, but that should be a separate change.

Differential Revision: http://reviews.llvm.org/D17184

llvm-svn: 262085
 2016-02-26 22:53:59 +00:00
Kostya Serebryany
503e17c728 [libFuzzer] add -print_final_stats=1 flag 
llvm-svn: 262084
 2016-02-26 22:42:23 +00:00
Simon Pilgrim
13e404ae07 Strip trailing whitespace. NFCI. 
llvm-svn: 262083
 2016-02-26 22:28:50 +00:00
Philip Reames
b6c3452142 [ConstantRange] Add umin/smin operators 
This was split off from http://reviews.llvm.org/D17184.

Reviewed by: Sanjoy

llvm-svn: 262080
 2016-02-26 22:08:18 +00:00
Kit Barton
f070e5e85c [PPC] Legalize FNEG on PPC when possible 
Currently we always expand ISD::FNEG. For v4f32 and v2f64 vector types VSX has
native support for this opcode

Phabricator: http://reviews.llvm.org/D17647
llvm-svn: 262079
 2016-02-26 21:59:44 +00:00
Simon Pilgrim
b240484d51 Fix spelling. NFCI. 
llvm-svn: 262078
 2016-02-26 21:56:27 +00:00
Sanjay Patel
014ad4d329 [x86, InstCombine] transform x86 AVX2 masked stores to LLVM intrinsics 
Replicate everything for integers...because x86.

Continuation of:
http://reviews.llvm.org/rL262064

llvm-svn: 262077
 2016-02-26 21:51:44 +00:00
Kostya Serebryany
a9a412139e [libFuzzer] initial implementation of path coverage based on -fsanitize-coverage=trace-pc. This does not scale well yet, but already cracks FullCoverageSetTest in seconds 
llvm-svn: 262073
 2016-02-26 21:33:56 +00:00
Kit Barton
e51a13ad8a Power9] Implement new vsx instructions: compare and conversion 
This change implements the following vsx instructions:

Quad/Double-Precision Compare:
xscmpoqp xscmpuqp
xscmpexpdp xscmpexpqp
xscmpeqdp xscmpgedp xscmpgtdp xscmpnedp
xvcmpnedp(.) xvcmpnesp(.)
Quad-Precision Floating-Point Conversion
xscvqpdp(o) xscvdpqp
xscvqpsdz xscvqpswz xscvqpudz xscvqpuwz xscvsdqp xscvudqp
xscvdphp xscvhpdp xvcvhpsp xvcvsphp
xsrqpi xsrqpix xsrqpxp
28 instructions

Phabricator: http://reviews.llvm.org/D16709
llvm-svn: 262068
 2016-02-26 21:11:55 +00:00
Sanjay Patel
d5185a0950 [x86, InstCombine] transform x86 AVX masked stores to LLVM intrinsics 
The intended effect of this patch in conjunction with:
http://reviews.llvm.org/rL259392
http://reviews.llvm.org/rL260145

is that customers using the AVX intrinsics in C will benefit from combines when
the store mask is constant:

void mstore_zero_mask(float *f, __m128 v) {
  _mm_maskstore_ps(f, _mm_set1_epi32(0), v);
}

void mstore_fake_ones_mask(float *f, __m128 v) {
  _mm_maskstore_ps(f, _mm_set1_epi32(1), v);
}

void mstore_ones_mask(float *f, __m128 v) {
  _mm_maskstore_ps(f, _mm_set1_epi32(0x80000000), v);
}

void mstore_one_set_elt_mask(float *f, __m128 v) {
  _mm_maskstore_ps(f, _mm_set_epi32(0x80000000, 0, 0, 0), v);
}

...so none of the above will actually generate a masked store for optimized code.

Differential Revision: http://reviews.llvm.org/D17485

llvm-svn: 262064
 2016-02-26 21:04:14 +00:00
Sanjay Patel
7e9bef055d [x86] refactor to eliminate duplicated code; NFCI 
llvm-svn: 262062
 2016-02-26 20:59:05 +00:00
Amaury Sechet
7a6818d710 Fix warning in DwarfCFIException. NFC 
llvm-svn: 262061
 2016-02-26 20:49:07 +00:00
Amaury Sechet
366f277273 Extract the method to begin and end a fragment in AsmPrinterHandler in their own method. NFC 
Summary: This is extracted from D17555

Reviewers: davidxl, reames, sanjoy, MatzeB, pete

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D17580

llvm-svn: 262058
 2016-02-26 20:30:37 +00:00
Quentin Colombet
e853dd8f93 [GlobalISel] Fix a ranlib warning about empty TOC. 
Fixes PR26733

llvm-svn: 262057
 2016-02-26 20:05:02 +00:00
Nirav Dave
9dd7b9a38b Fix Sparc 32bit Lowering to rebundle up v2i32 values. 
Summary: Fix LowerCall to rebundle v2i32 values after lowering and add testcase

Reviewers: jyknight

Subscribers: llvm-commits, jyknight

Differential Revision: http://reviews.llvm.org/D17615

llvm-svn: 262048
 2016-02-26 18:55:22 +00:00
Sanjay Patel
9bf70679ba [x86, AVX] fold 'isPositive' 256-bit vector integer operations (PR26701) 
This extends the fold introduced with:
http://reviews.llvm.org/rL262036

llvm-svn: 262047
 2016-02-26 18:42:50 +00:00
Reid Kleckner
b798ad869b [IR] Optimize bitfield layout of Value for MSVC 
This should save a pointer of padding from all MSVC Value subclasses.

Recall that MSVC will not pack the following bitfields together:
  unsigned Bits : 29;
  unsigned Flag1 : 1;
  unsigned Flag2 : 1;
  unsigned Flag3 : 1;

Add a static_assert because LLVM developers always trip over this
behavior. This regressed in June.

llvm-svn: 262045
 2016-02-26 18:08:59 +00:00
Renato Golin
b62da81886 [CMAKE] Update build on recent Haiku 
This patch updates cmake build scripts to build on Haiku. It adds Haiku x86_64 to config.guess.
Please consider reviewing.

Pathc by Jérôme Duval.

llvm-svn: 262038
 2016-02-26 17:01:45 +00:00
Sanjay Patel
705cd39feb [x86, SSE] fold 'isPositive' vector integer operations (PR26701) 
This is one of the cases shown in:
https://llvm.org/bugs/show_bug.cgi?id=26701

Shift and negate is what InstCombine appears to prefer, so I've started with that pattern. 
Note that the 'pcmpeq' instructions are always generating the negative one for the actual
'pcmpgt' comparison in each case (side note: why isn't there an alias mnemonic for that?).

Differential Revision: http://reviews.llvm.org/D17630

llvm-svn: 262036
 2016-02-26 16:56:03 +00:00
Reid Kleckner
9896740471 [WinEH] Fix funclet return block clobber mask placement 
MBB slot index intervals are half open, not closed. getMBBEndIndex()
returns the slot index of the start of the next block in layout order.
Placing a register mask there is incorrect if the successor of the
funclet return is not laid out after the return. Clang generates IR for
catch bodies before generating the following normal code, so we never
noticed this issue until the D frontend authors filed a bug about it.

Instead, we can put the clobber mask on the last instruction of the
funclet return block. We still aren't using a register mask operand on
the CATCHRET instruction because it would cause PEI to spill all CSRs,
including XMM regs, in the prologue.

Fixes PR26679.

llvm-svn: 262035
 2016-02-26 16:53:19 +00:00
Chandler Carruth
a1c2c4d774 [PM] Finish removing references to fix MSVC builds. Somehow adding base 
classes changed whether the decltype of these expressions was
a reference. I'm somewhat horrified why, and there may need to be
a deeper fix on MSVC, but this should at least get the bots a step
further.

llvm-svn: 262008
 2016-02-26 12:30:18 +00:00
Chris Dewhurst
1127527bb7 Reverting breaking change. Sorry. 
llvm-svn: 262007
 2016-02-26 12:20:10 +00:00
Chandler Carruth
a6f6de1689 [PM] Speculative patch to try and fix MSVC's compilation. 
No idea why r262004 triggered this, but just trying to fix somehow.

llvm-svn: 262006
 2016-02-26 12:17:54 +00:00
Chris Dewhurst
5c895f8b77 Reviewed at reviews.llvm.org/D17133 
llvm-svn: 262005
 2016-02-26 11:46:47 +00:00
Chandler Carruth
a25189ea0f [PM] Introduce CRTP mixin base classes to help define passes and 
analyses in the new pass manager.

These just handle really basic stuff: turning a type name into a string
statically that is nice to print in logs, and getting a static unique ID
for each analysis.

Sadly, the format of passes in anonymous namespaces makes using their
names in tests really annoying so I've customized the names of the no-op
passes to keep tests sane to read.

This is the first of a few simplifying refactorings for the new pass
manager that should reduce boilerplate and confusion.

llvm-svn: 262004
 2016-02-26 11:44:45 +00:00
Chris Dewhurst
a09327f2ce Initial test commit only 
llvm-svn: 262003
 2016-02-26 11:38:24 +00:00
Nikolay Haustov
2aef2157de [AMDGPU] Assembler: Basic support for MIMG 
Add parsing and printing of image operands. Matches legacy sp3 assembler.
Change image instruction order to have data/image/sampler operands in the beginning. This is needed because optional operands in MC are always last.
Update SITargetLowering for new order.
Add basic MC test.
Update CodeGen tests.

Review: http://reviews.llvm.org/D17574
llvm-svn: 261995
 2016-02-26 09:51:05 +00:00
James Molloy
effcf0180f [AArch64] Slight cleanup in FPLoadBalancing 
Instead of the convoluted if-statment we can just use getColor. This also fixes
a bug where we relied upon the parity of tablegen-generated register indexes
(instead of using the machine encoding).

llvm-svn: 261990
 2016-02-26 09:10:53 +00:00
Craig Topper
fa194ccc73 [X86] Null out some redundant patterns for masked vector register to register moves. These can be accomplished with both aligned and unaligned opcodes. 
Currently aligned is what is being used so remove the redundant patterns for the unaligned versions. But don't do this for the byte and word vector types since they don't have aligned versions.

llvm-svn: 261985
 2016-02-26 06:50:29 +00:00
Craig Topper
153dfdd2c9 [TableGen] Fix typos in comments. NFC 
llvm-svn: 261984
 2016-02-26 06:50:27 +00:00
Craig Topper
3a6e292b6d [X86] Add test cases for r261977 and fix a grammatical error. 
llvm-svn: 261983
 2016-02-26 06:50:24 +00:00
Haicheng Wu
5511101c3f [JumpThreading] Simplify Instructions first in ComputeValueKnownInPredecessors() 
This change tries to find more opportunities to thread over basic blocks.

llvm-svn: 261981
 2016-02-26 06:06:04 +00:00
Craig Topper
29e5870acb [X86] Remove a couple returns after llvm_unreachables. NFC 
llvm-svn: 261979
 2016-02-26 05:29:39 +00:00
Craig Topper
f1c180e526 [X86] Use inclusive ranges for XMM/YMM/ZMM registers in is32Extended and isX86_64ExtendedReg. NFC 
llvm-svn: 261978
 2016-02-26 05:29:35 +00:00
Craig Topper
e52def5593 [X86] Explicitly diagnose use of %xmm16-%xmm31, %ymm16-%ymm31 and %zmm16-%zmm31 when AVX512 is not enabled in the asm parser. 
llvm-svn: 261977
 2016-02-26 05:29:32 +00:00
Matthias Braun
4033884b97 MachineCopyPropagation: Catch copies of the form A<-B;A<-B 
Differential Revision: http://reviews.llvm.org/D17475

llvm-svn: 261966
 2016-02-26 03:18:55 +00:00
Matthias Braun
7c163b2f7d MachineCopyPropagation: Keep scanning through instructions with regmasks 
This also simplifies the code by removing the overly conservative
NoInterveningSideEffect() function. This function checked:
- That the two copies belong to the same block: We only process one
  block at a time and clear our maps in between it is impossible to find a
  copy from a different block.
- There is no terminator between the two copy instructions: This is not
  allowed anyway (the MachineVerifier would complain)
- Does not have instructions with hasUnmodeledSideEffects() or isCall()
  set: Even for those instructuction we must have all clobbers/defs of
  registers explicit as an operand. If the register is explicitely
  clobbered we would never come to the point of checking for
  NoInterveningSideEffect() anyway.

(I also checked this with a temporary build of the test-suite with all
 potentially failing conditions in NoInterveningSideEffect() turned into
 asserts)

Differential Revision: http://reviews.llvm.org/D17474

llvm-svn: 261965
 2016-02-26 03:18:50 +00:00
Michael Zolotukhin
4826fdb5cd [LoopUnrollAnalyzer] Check that we're using SCEV for the same loop we're simulating. 
Summary: Check that we're using SCEV for the same loop we're simulating. Otherwise, we might try to use the iteration number of the current loop in SCEV expressions for inner/outer loops IVs, which is clearly incorrect.

Reviewers: chandlerc, hfinkel

Subscribers: sanjoy, llvm-commits, mzolotukhin

Differential Revision: http://reviews.llvm.org/D17632

llvm-svn: 261958
 2016-02-26 02:57:05 +00:00
Junmo Park
527d68963a Minor code cleanups. NFC. 
llvm-svn: 261955
 2016-02-26 02:07:36 +00:00
Mike Aizatsky
b65bb6da73 [sancov] Pruning full dominator blocks from instrumentation. 
Summary:
This is the first simple attempt to reduce number of coverage-
instrumented blocks.

If a basic block dominates all its successors, then its coverage
information is useless to us. Ingore such blocks if
santizer-coverage-prune-tree option is set.

Differential Revision: http://reviews.llvm.org/D17626

llvm-svn: 261949
 2016-02-26 01:17:22 +00:00
David Majnemer
473ae5e981 [WinEH] Don't remove unannotated inline-asm calls 
Inline-asm calls aren't annotated with funclet bundle operands because
they don't throw and cannot be inlined through.  We shouldn't require
them to bear an funclet bundle operand.

llvm-svn: 261942
 2016-02-26 00:04:25 +00:00
David L Kreitzer
9eac7219b8 Reformatted a comment to fit the 80 column limit. NFC. 
llvm-svn: 261916
 2016-02-25 18:50:45 +00:00
Hongbin Zheng
f0c9856bf9 Introduce RegionInfoAnalysis, which compute Region Tree in the new PassManager. NFC 
Differential Revision: http://reviews.llvm.org/D17571

llvm-svn: 261904
 2016-02-25 17:54:25 +00:00
Hongbin Zheng
e391b241c7 Introduce DominanceFrontierAnalysis to the new PassManager to compute DominanceFrontier. NFC 
Differential Revision: http://reviews.llvm.org/D17570

llvm-svn: 261903
 2016-02-25 17:54:15 +00:00
Hongbin Zheng
3e75d3d4e5 Introduce analysis pass to compute PostDominators in the new pass manager. NFC 
Differential Revision: http://reviews.llvm.org/D17537

llvm-svn: 261902
 2016-02-25 17:54:07 +00:00
Tim Northover
50249c2bb2 ARM: disallow pc as a base register in Thumb2 memory ops. 
These should all be deferring to the "OP (literal)" variant according to the
ARM ARM.

llvm-svn: 261895
 2016-02-25 16:54:52 +00:00
Hongbin Zheng
3d17e7bc47 Revert "Introduce analysis pass to compute PostDominators in the new pass manager. NFC" 
This reverts commit a3e5cc6a51ab5ad88d1760c63284294a4e34c018.

llvm-svn: 261891
 2016-02-25 16:45:53 +00:00
Hongbin Zheng
b446bc1e4f Revert "Introduce DominanceFrontierAnalysis to the new PassManager to compute DominanceFrontier. NFC" 
This reverts commit 109c38b2226a87b0be73fa7a0a8c1a81df20aeb2.

llvm-svn: 261890
 2016-02-25 16:45:46 +00:00
Hongbin Zheng
4f423eca95 Revert "Introduce RegionInfoAnalysis, which compute Region Tree in the new PassManager. NFC" 
This reverts commit 8228b4d374edeb4cc0c5fddf6e1ab876918ee126.

llvm-svn: 261889
 2016-02-25 16:45:37 +00:00
Sanjay Patel
699293f9ca rangify; NFCI 
llvm-svn: 261888
 2016-02-25 16:44:27 +00:00
Geoff Berry
ef03e5a8d3 [AArch64] Clean up callee-save CFI emission. NFC. 
Summary:
Avoid special case for FP, LR CFI emission and just allow general
AArch64FrameLowering::emitCalleeSavedFrameMoves() to handle them.  Also,
stop recalculating the stack offsets in emitCalleeSavedFrameMoves()
since we can just reuse the previously calculated offset stored in the
MachineFrameInfo.

Depends on D17000

Reviewers: t.p.northover, rengolin, mcrosier, jmolloy

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D17004

llvm-svn: 261885
 2016-02-25 16:36:08 +00:00
Hongbin Zheng
4a56a70d94 Introduce RegionInfoAnalysis, which compute Region Tree in the new PassManager. NFC 
Differential Revision: http://reviews.llvm.org/D17571

llvm-svn: 261884
 2016-02-25 16:33:26 +00:00
Hongbin Zheng
10a5a19fa0 Introduce DominanceFrontierAnalysis to the new PassManager to compute DominanceFrontier. NFC 
Differential Revision: http://reviews.llvm.org/D17570

llvm-svn: 261883
 2016-02-25 16:33:15 +00:00
Hongbin Zheng
26e597b0c3 Introduce analysis pass to compute PostDominators in the new pass manager. NFC 
Differential Revision: http://reviews.llvm.org/D17537

llvm-svn: 261882
 2016-02-25 16:33:06 +00:00
Nikolay Haustov
b57a0b698b [AMDGPU] Disassembler: Support for all VOP1 instructions. 
Support all instructions with VOP1 encoding with 32 or 64-bit operands for VI subtarget:

VGPR_32 and VReg_64 operand register classes
VS_32 and VS_64 operand register classes with inline and literal constants
Tests for VOP1 instructions.

Patch by: skolton

Reviewers: arsenm, tstellarAMD

Review: http://reviews.llvm.org/D17194
llvm-svn: 261878
 2016-02-25 16:09:14 +00:00
Igor Breger
c2763588ac AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . Change memory operand parser handling. 
Differential Revision: http://reviews.llvm.org/D17564

llvm-svn: 261862
 2016-02-25 13:30:17 +00:00
Hrvoje Varga
a7d72fcec9 [mips][microMIPS] Implement DINSU, DINSM, DINS instructions 
Differential Revision: http://reviews.llvm.org/D16181

llvm-svn: 261860
 2016-02-25 12:53:29 +00:00
Nikolay Haustov
f6baecf637 [AMDGPU] Assembler: Simplify handling of optional operands 
Resubmit with index problem fixed. Verified with valgrind.

Prepare to support DPP encodings.

For DPP encodings, we want row_mask/bank_mask/bound_ctrl to be optional operands.
However this means that when parsing instruction which has no mnemonic prefix,
we cannot add both default values for VOP3 and for DPP optional operands
to OperandVector - neither instructions would match. So add default values
for optional operands to MCInst during conversion instead.

Mark more operands as IsOptional = 1 in .td files.
Do not add default values for optional operands to OperandVector in AMDGPUAsmParser.
Add default values for optional operands during conversion using new helper addOptionalImmOperand.
Change to cvtVOP3_2_mod to check instruction flag instead of presence of modifiers. In the future, cvtVOP3* functions can be combined into one.
Separate cvtFlat and cvtFlatAtomic.
Fix CNDMASK_B32 definition to have no modifiers.

Review: http://reviews.llvm.org/D17445
llvm-svn: 261856
 2016-02-25 10:58:54 +00:00
Simon Pilgrim
67f60b197d [X86][SSE3] Added combine support for MOVDDUP/MOVSHDUP/MOVSLDUP target shuffles 
Now that PerformShuffleCombine can handle unary shuffles.

llvm-svn: 261843
 2016-02-25 09:12:12 +00:00
NAKAMURA Takumi
71379d5304 Revert r261742, "[AMDGPU] Assembler: Simplify handling of optional operands" 
It brought undefined behavior.

llvm-svn: 261839
 2016-02-25 08:35:27 +00:00
Justin Bogner
5af532d89d PM: Implement a basic loop pass manager 
This creates the new-style LoopPassManager and wires it up with dummy
and print passes.

This version doesn't support modifying the loop nest at all. It will
be far easier to discuss and evaluate the approaches to that with this
in place so that the boilerplate is out of the way.

llvm-svn: 261831
 2016-02-25 07:23:08 +00:00
Elena Demikhovsky
b3f8b2cb2e Optimized loading (zextload) of i1 value from memory. 
This patch is a partial revert of https://llvm.org/svn/llvm-project/llvm/trunk@237793.
Extra "and" causes performance degradation.

We assume that i1 is stored in zero-extended form. And store operation is responsible for zeroing upper bits.

Differential Revision: http://reviews.llvm.org/D17541

llvm-svn: 261828
 2016-02-25 07:05:12 +00:00
Justin Bogner
24f8ffc3c6 IR: Make the X / undef -> undef fold match the comment 
The constant folding for sdiv and udiv has a big discrepancy between the
comments and the code, which looks like a typo. Currently, we're folding
X / undef pretty inconsistently:

  0 / undef -> undef
  C / undef -> 0
  undef / undef -> 0

Whereas the comments state we do X / undef -> undef. The logic that
returns zero is actually commented as doing undef / X -> 0, despite that
the LHS isn't undef in many of the cases that hit it.

llvm-svn: 261813
 2016-02-25 01:02:18 +00:00
Junmo Park
e684ff35db [CodeGenPrepare] Remove load-based heuristic 
Summary:
Both the hardware and LLVM have changed since 2012.
Now, load-based heuristic don't show big differences any more on OoO cores.

There is no notable regressons and improvements on spec2000/2006. (Cortex-A57, Core i5).

Reviewers: spatel, zansari
    
Differential Revision: http://reviews.llvm.org/D16836

llvm-svn: 261809
 2016-02-25 00:23:27 +00:00
Cong Hou
6af13323da Detecte vector reduction operations just before instruction selection. 
(This is the second attemp to commit this patch, after fixing pr26652 & pr26653).

This patch detects vector reductions before instruction selection. Vector
reductions are vectorized reduction operations, and for such operations we have
freedom to reorganize the elements of the result as long as the reduction of them
stay unchanged. This will enable some reduction pattern recognition during
instruction combine such as SAD/dot-product on X86. A flag is added to
SDNodeFlags to mark those vector reduction nodes to be checked during instruction
combine.

To detect those vector reductions, we search def-use chains starting from the
given instruction, and check if all uses fall into two categories:

1. Reduction with another vector.
2. Reduction on all elements.

in which 2 is detected by recognizing the pattern that the loop vectorizer
generates to reduce all elements in the vector outside of the loop, which
includes several ShuffleVector and one ExtractElement instructions.


Differential revision: http://reviews.llvm.org/D15250

llvm-svn: 261804
 2016-02-24 23:40:36 +00:00
Amaury Sechet
7446ce3b8d Add capability to push/pop DFI in MCStreamer. NFC 
Summary: This is extracted from D17555

Reviewers: davidxl, reames, sanjoy, MatzeB, pete

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D17579

llvm-svn: 261796
 2016-02-24 22:25:18 +00:00
Anna Zaks
22dfbced29 [asan] Do not instrument globals in the special "LLVM" sections 
llvm-svn: 261794
 2016-02-24 22:12:18 +00:00
Matthias Braun
33cae27aaa MachineInstr: Respect register aliases in clearRegiserKills() 
This fixes bugs in copy elimination code in llvm. It slightly changes the
semantics of clearRegisterKills(). This is appropriate because:
- Users in lib/CodeGen/MachineCopyPropagation.cpp and
  lib/Target/AArch64RedundantCopyElimination.cpp and
  lib/Target/SystemZ/SystemZElimCompare.cpp are incorrect without it
  (see included testcase).
- All other users in llvm are unaffected (they pass TRI==nullptr)
- (Kill flags are optional anyway so removing too many shouldn't hurt.)

Differential Revision: http://reviews.llvm.org/D17554

llvm-svn: 261763
 2016-02-24 19:21:48 +00:00
Tim Northover
681f4f01b7 AArch64: remove CRC feature from Cyclone. 
Turns out we don't actually support those instructions.

llvm-svn: 261759
 2016-02-24 18:10:17 +00:00
Teresa Johnson
d364501c91 [ThinLTO] Add missing breaks when parsing summaries (NFC) 
This wasn't causing a correctness issue, but was causing extra duplicate
entries to be added to the SummaryMap.

llvm-svn: 261757
 2016-02-24 17:57:28 +00:00
David Majnemer
f106ac635e [SimplifyCFG] Use a more elegant solution than r261731 
The cleanupret instruction has an invariant that it's 'from' operand be
a cleanuppad.  This invariant was violated when we removed a dead block
which removed a cleanuppad leaving behind a cleanupret with an undef
'from' operand.

This was solved in r261731 by staving off the removal of the dead block
to a later pass.

However, it occured to me that we do not need to do this.
Instead, we can simply avoid processing the cleanupret if it has an
undef 'from' operand because we know that it will be removed soon.

llvm-svn: 261754
 2016-02-24 17:30:48 +00:00
Sanjay Patel
97801c676a [InstCombine] enable optimization of casted vector xor instructions 
This is part of the payoff for the refactoring in:
http://reviews.llvm.org/rL261649
http://reviews.llvm.org/rL261707

In addition to removing a pile of duplicated code, the xor case was
missing the optimization for vector types because it checked
"SrcTy->isIntegerTy()" rather than "SrcTy->isIntOrIntVectorTy()"
like 'and' and 'or' were already doing.

This solves part of:
https://llvm.org/bugs/show_bug.cgi?id=26702

llvm-svn: 261750
 2016-02-24 17:00:34 +00:00
Anton Korobeynikov
173f5d7e53 MSP430InstrInfo::loadRegFromStackSlot forgets to set register def. 
Summary:
For instance, compiling the below results in a panic:

```
llc: ../lib/CodeGen/InlineSpiller.cpp:1140: bool (anonymous namespace)::InlineSpiller::foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned int> >, llvm::MachineInstr *): Assertion `MO->isDead() && "Cannot fold physreg def"' failed.
#0 0x00007f50fbcf353e llvm::sys::PrintStackTrace(llvm::raw_ostream&) /home/h/3rd/llvm/build/../lib/Support/Unix/Signals.inc:321:15
#1 0x00007f50fbcf3929 PrintStackTraceSignalHandler(void*) /home/h/3rd/llvm/build/../lib/Support/Unix/Signals.inc:380:1
#2 0x00007f50fbcf22a3 llvm::sys::RunSignalHandlers() /home/h/3rd/llvm/build/../lib/Support/Signals.cpp:45:5
#3 0x00007f50fbcf3bb4 SignalHandler(int) /home/h/3rd/llvm/build/../lib/Support/Unix/Signals.inc:210:1
#4 0x00007f50fa87a180 (/lib/x86_64-linux-gnu/libc.so.6+0x35180)
#5 0x00007f50fa87a107 gsignal (/lib/x86_64-linux-gnu/libc.so.6+0x35107)
#6 0x00007f50fa87b4e8 abort (/lib/x86_64-linux-gnu/libc.so.6+0x364e8)
#7 0x00007f50fa873226 (/lib/x86_64-linux-gnu/libc.so.6+0x2e226)
#8 0x00007f50fa8732d2 (/lib/x86_64-linux-gnu/libc.so.6+0x2e2d2)
#9 0x00007f50fddd9287 (anonymous namespace)::InlineSpiller::foldMemoryOperand(llvm::ArrayRef<std::pair<llvm::MachineInstr*, unsigned int> >, llvm::MachineInstr*) /home/h/3rd/llvm/build/../lib/CodeGen/InlineSpiller.cpp:1141:21
#10 0x00007f50fddd9ee9 (anonymous namespace)::InlineSpiller::spillAroundUses(unsigned int) /home/h/3rd/llvm/build/../lib/CodeGen/InlineSpiller.cpp:1286:9
#11 0x00007f50fddd388b (anonymous namespace)::InlineSpiller::spillAll() /home/h/3rd/llvm/build/../lib/CodeGen/InlineSpiller.cpp:1338:21
#12 0x00007f50fddd221d (anonymous namespace)::InlineSpiller::spill(llvm::LiveRangeEdit&) /home/h/3rd/llvm/build/../lib/CodeGen/InlineSpiller.cpp:1391:3
#13 0x00007f50fdfd921b (anonymous namespace)::RAGreedy::selectOrSplitImpl(llvm::LiveInterval&, llvm::SmallVectorImpl<unsigned int>&, llvm::SmallSet<unsigned int, 16u, std::less<unsigned int> >&, unsigned int) /home/h/3rd/llvm/build/../lib/CodeGen/RegAllocGreedy.cpp:2555:5
#14 0x00007f50fdfd647b (anonymous namespace)::RAGreedy::selectOrSplit(llvm::LiveInterval&, llvm::SmallVectorImpl<unsigned int>&) /home/h/3rd/llvm/build/../lib/CodeGen/RegAllocGreedy.cpp:2221:12
#15 0x00007f50fdfc89f9 llvm::RegAllocBase::allocatePhysRegs() /home/h/3rd/llvm/build/../lib/CodeGen/RegAllocBase.cpp:110:14
#16 0x00007f50fdfd6337 (anonymous namespace)::RAGreedy::runOnMachineFunction(llvm::MachineFunction&) /home/h/3rd/llvm/build/../lib/CodeGen/RegAllocGreedy.cpp:2611:3
#17 0x00007f50fded33ee llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /home/h/3rd/llvm/build/../lib/CodeGen/MachineFunctionPass.cpp:43:3
#18 0x00007f50fd6cdc6f llvm::FPPassManager::runOnFunction(llvm::Function&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1550:23
#19 0x00007f50fd6cdf85 llvm::FPPassManager::runOnModule(llvm::Module&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1571:16
#20 0x00007f50fd6ce71a (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1627:23
#21 0x00007f50fd6ce246 llvm::legacy::PassManagerImpl::run(llvm::Module&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1730:16
#22 0x00007f50fd6cec31 llvm::legacy::PassManager::run(llvm::Module&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1761:3
#23 0x0000000000415bdc compileModule(char**, llvm::LLVMContext&) /home/h/3rd/llvm/build/../tools/llc/llc.cpp:405:5
#24 0x0000000000414571 main /home/h/3rd/llvm/build/../tools/llc/llc.cpp:211:13
#25 0x00007f50fa866b45 __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x21b45)
#26 0x0000000000414296 _start (/home/h/3rd/llvm/build/bin/llc+0x414296)
Stack dump:
0.	Program arguments: ./bin/llc -mtriple msp430 loadstore.ll 
1.	Running pass 'Function Pass Manager' on module 'loadstore.ll'.
2.	Running pass 'Greedy Register Allocator' on function '@inc'
```

Original IR:

```llvm
%struct.VeryLarge = type { i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: norecurse nounwind
define void @inc(%struct.VeryLarge* noalias nocapture sret %agg.result, %struct.VeryLarge* byval align 1 %s) #0 {
entry:
  %p0 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 0
  %0 = load i8, i8* %p0, align 1, !tbaa !1
  %p1 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 1
  %1 = load i32, i32* %p1, align 1, !tbaa !6
  %p2 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 2
  %2 = load i32, i32* %p2, align 1, !tbaa !7
  %p3 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 3
  %3 = load i32, i32* %p3, align 1, !tbaa !8
  %p4 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 4
  %4 = load i32, i32* %p4, align 1, !tbaa !9
  %p5 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 5
  %5 = load i32, i32* %p5, align 1, !tbaa !10
  %p6 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 6
  %6 = load i32, i32* %p6, align 1, !tbaa !11
  %p7 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 7
  %7 = load i32, i32* %p7, align 1, !tbaa !12
  %p8 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 8
  %8 = load i32, i32* %p8, align 1, !tbaa !13
  %p9 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 9
  %9 = load i32, i32* %p9, align 1, !tbaa !14
  %p10 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 10
  %10 = load i32, i32* %p10, align 1, !tbaa !15
  %p11 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 11
  %11 = load i32, i32* %p11, align 1, !tbaa !16
  %p12 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 12
  %12 = load i32, i32* %p12, align 1, !tbaa !17
  %p13 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 13
  %13 = load i32, i32* %p13, align 1, !tbaa !18
  %p14 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 14
  %14 = load i32, i32* %p14, align 1, !tbaa !19
  %p15 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 15
  %15 = load i32, i32* %p15, align 1, !tbaa !20
  %p16 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 16
  %16 = load i32, i32* %p16, align 1, !tbaa !21
  %p17 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 17
  %17 = load i32, i32* %p17, align 1, !tbaa !22
  %p18 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 18
  %18 = load i32, i32* %p18, align 1, !tbaa !23
  %p19 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 19
  %19 = load i32, i32* %p19, align 1, !tbaa !24
  %p20 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 20
  %20 = load i32, i32* %p20, align 1, !tbaa !25
  %p21 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 21
  %21 = load i32, i32* %p21, align 1, !tbaa !26
  %p22 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 22
  %22 = load i32, i32* %p22, align 1, !tbaa !27
  %p23 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 23
  %23 = load i32, i32* %p23, align 1, !tbaa !28
  %p24 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 24
  %24 = load i32, i32* %p24, align 1, !tbaa !29
  %p25 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 25
  %25 = load i32, i32* %p25, align 1, !tbaa !30
  %p26 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 26
  %26 = load i32, i32* %p26, align 1, !tbaa !31
  %p27 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 27
  %27 = load i32, i32* %p27, align 1, !tbaa !32
  %p28 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 28
  %28 = load i32, i32* %p28, align 1, !tbaa !33
  %p29 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 29
  %29 = load i32, i32* %p29, align 1, !tbaa !34
  %p30 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 30
  %30 = load i32, i32* %p30, align 1, !tbaa !35
  %p31 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 31
  %31 = load i32, i32* %p31, align 1, !tbaa !36
  %p32 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 32
  %32 = load i32, i32* %p32, align 1, !tbaa !37
  %add = add i8 %0, 1
  store i8 %add, i8* %p0, align 1, !tbaa !1
  %add2 = add i32 %1, 2
  store i32 %add2, i32* %p1, align 1, !tbaa !6
  %add3 = add i32 %2, 3
  store i32 %add3, i32* %p2, align 1, !tbaa !7
  %add4 = add i32 %3, 4
  store i32 %add4, i32* %p3, align 1, !tbaa !8
  %add5 = add i32 %4, 5
  store i32 %add5, i32* %p4, align 1, !tbaa !9
  %add6 = add i32 %5, 6
  store i32 %add6, i32* %p5, align 1, !tbaa !10
  %add7 = add i32 %6, 7
  store i32 %add7, i32* %p6, align 1, !tbaa !11
  %add8 = add i32 %7, 8
  store i32 %add8, i32* %p7, align 1, !tbaa !12
  %add9 = add i32 %8, 9
  store i32 %add9, i32* %p8, align 1, !tbaa !13
  %add10 = add i32 %9, 10
  store i32 %add10, i32* %p9, align 1, !tbaa !14
  %add11 = add i32 %10, 11
  store i32 %add11, i32* %p10, align 1, !tbaa !15
  %add12 = add i32 %11, 12
  store i32 %add12, i32* %p11, align 1, !tbaa !16
  %add13 = add i32 %12, 13
  store i32 %add13, i32* %p12, align 1, !tbaa !17
  %add14 = add i32 %13, 14
  store i32 %add14, i32* %p13, align 1, !tbaa !18
  %add15 = add i32 %14, 15
  store i32 %add15, i32* %p14, align 1, !tbaa !19
  %add16 = add i32 %15, 16
  store i32 %add16, i32* %p15, align 1, !tbaa !20
  %add17 = add i32 %16, 17
  store i32 %add17, i32* %p16, align 1, !tbaa !21
  %add18 = add i32 %17, 18
  store i32 %add18, i32* %p17, align 1, !tbaa !22
  %add19 = add i32 %18, 19
  store i32 %add19, i32* %p18, align 1, !tbaa !23
  %add20 = add i32 %19, 20
  store i32 %add20, i32* %p19, align 1, !tbaa !24
  %add21 = add i32 %20, 21
  store i32 %add21, i32* %p20, align 1, !tbaa !25
  %add22 = add i32 %21, 22
  store i32 %add22, i32* %p21, align 1, !tbaa !26
  %add23 = add i32 %22, 23
  store i32 %add23, i32* %p22, align 1, !tbaa !27
  %add24 = add i32 %23, 24
  store i32 %add24, i32* %p23, align 1, !tbaa !28
  %add25 = add i32 %24, 25
  store i32 %add25, i32* %p24, align 1, !tbaa !29
  %add26 = add i32 %25, 26
  store i32 %add26, i32* %p25, align 1, !tbaa !30
  %add27 = add i32 %26, 27
  store i32 %add27, i32* %p26, align 1, !tbaa !31
  %add28 = add i32 %27, 28
  store i32 %add28, i32* %p27, align 1, !tbaa !32
  %add29 = add i32 %28, 29
  store i32 %add29, i32* %p28, align 1, !tbaa !33
  %add30 = add i32 %29, 30
  store i32 %add30, i32* %p29, align 1, !tbaa !34
  %add31 = add i32 %30, 31
  store i32 %add31, i32* %p30, align 1, !tbaa !35
  %add32 = add i32 %31, 32
  store i32 %add32, i32* %p31, align 1, !tbaa !36
  %add33 = add i32 %32, 33
  store i32 %add33, i32* %p32, align 1, !tbaa !37
  %33 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %agg.result, i32 0, i32 0
  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %33, i8* %p0, i32 129, i32 1, i1 false), !tbaa.struct !38
  ret void
}

; Function Attrs: argmemonly nounwind
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #1

attributes #0 = { norecurse nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { argmemonly nounwind }

!llvm.ident = !{!0}

!0 = !{!"clang version 3.8.0 (git://github.com/llvm-mirror/clang 40ef2b7531472c41212c4719a9294aeb7bddebbc) (git://github.com/llvm-mirror/llvm c601eaf55606dfb9ad372b514b77aa00d1409be1)"}
!1 = !{!2, !3, i64 0}
!2 = !{!"", !3, i64 0, !5, i64 1, !5, i64 5, !5, i64 9, !5, i64 13, !5, i64 17, !5, i64 21, !5, i64 25, !5, i64 29, !5, i64 33, !5, i64 37, !5, i64 41, !5, i64 45, !5, i64 49, !5, i64 53, !5, i64 57, !5, i64 61, !5, i64 65, !5, i64 69, !5, i64 73, !5, i64 77, !5, i64 81, !5, i64 85, !5, i64 89, !5, i64 93, !5, i64 97, !5, i64 101, !5, i64 105, !5, i64 109, !5, i64 113, !5, i64 117, !5, i64 121, !5, i64 125}
!3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"}
!5 = !{!"int", !3, i64 0}
!6 = !{!2, !5, i64 1}
!7 = !{!2, !5, i64 5}
!8 = !{!2, !5, i64 9}
!9 = !{!2, !5, i64 13}
!10 = !{!2, !5, i64 17}
!11 = !{!2, !5, i64 21}
!12 = !{!2, !5, i64 25}
!13 = !{!2, !5, i64 29}
!14 = !{!2, !5, i64 33}
!15 = !{!2, !5, i64 37}
!16 = !{!2, !5, i64 41}
!17 = !{!2, !5, i64 45}
!18 = !{!2, !5, i64 49}
!19 = !{!2, !5, i64 53}
!20 = !{!2, !5, i64 57}
!21 = !{!2, !5, i64 61}
!22 = !{!2, !5, i64 65}
!23 = !{!2, !5, i64 69}
!24 = !{!2, !5, i64 73}
!25 = !{!2, !5, i64 77}
!26 = !{!2, !5, i64 81}
!27 = !{!2, !5, i64 85}
!28 = !{!2, !5, i64 89}
!29 = !{!2, !5, i64 93}
!30 = !{!2, !5, i64 97}
!31 = !{!2, !5, i64 101}
!32 = !{!2, !5, i64 105}
!33 = !{!2, !5, i64 109}
!34 = !{!2, !5, i64 113}
!35 = !{!2, !5, i64 117}
!36 = !{!2, !5, i64 121}
!37 = !{!2, !5, i64 125}
!38 = !{i64 0, i64 1, !39, i64 1, i64 4, !40, i64 5, i64 4, !40, i64 9, i64 4, !40, i64 13, i64 4, !40, i64 17, i64 4, !40, i64 21, i64 4, !40, i64 25, i64 4, !40, i64 29, i64 4, !40, i64 33, i64 4, !40, i64 37, i64 4, !40, i64 41, i64 4, !40, i64 45, i64 4, !40, i64 49, i64 4, !40, i64 53, i64 4, !40, i64 57, i64 4, !40, i64 61, i64 4, !40, i64 65, i64 4, !40, i64 69, i64 4, !40, i64 73, i64 4, !40, i64 77, i64 4, !40, i64 81, i64 4, !40, i64 85, i64 4, !40, i64 89, i64 4, !40, i64 93, i64 4, !40, i64 97, i64 4, !40, i64 101, i64 4, !40, i64 105, i64 4, !40, i64 109, i64 4, !40, i64 113, i64 4, !40, i64 117, i64 4, !40, i64 121, i64 4, !40, i64 125, i64 4, !40}
!39 = !{!3, !3, i64 0}
!40 = !{!5, !5, i64 0}
```



Reviewers: asl

Subscribers: qcolombet

Differential Revision: http://reviews.llvm.org/D17441

llvm-svn: 261746
 2016-02-24 15:15:02 +00:00
Simon Pilgrim
9dfc61c3a6 [X86][SSE41] Combine vector blends with zero 
Part 2 of 2
This patch add support for combining target shuffles into blends-with-zero.

Differential Revision: http://reviews.llvm.org/D17483

llvm-svn: 261745
 2016-02-24 15:14:21 +00:00
Simon Pilgrim
21285b3ce4 [X86][SSE41] Combine insertion of zero scalars into vector blends with zero 
Part 1 of 2
This patch attempts to replace the insertion of zero scalars with a vector blend with zero, avoiding the use of the integer insertion instructions (which are particularly slow on many targets).
(Part 2 will add support for combining multiple blends-with-zero).

Differential Revision: http://reviews.llvm.org/D17483

llvm-svn: 261743
 2016-02-24 14:53:27 +00:00
Nikolay Haustov
c13c21ef6e [AMDGPU] Assembler: Simplify handling of optional operands 
Prepare to support DPP encodings.

For DPP encodings, we want row_mask/bank_mask/bound_ctrl to be optional operands. However this means that when parsing instruction which has no mnemonic prefix, we cannot add both default values for VOP3 and for DPP optional operands to OperandVector - neither instructions would match. So add default values for optional operands to MCInst during conversion instead.

Mark more operands as IsOptional = 1 in .td files.
Do not add default values for optional operands to OperandVector in AMDGPUAsmParser.
Add default values for optional operands during conversion using new helper addOptionalImmOperand.
Change to cvtVOP3_2_mod to check instruction flag instead of presence of modifiers. In the future, cvtVOP3* functions can be combined into one.
Separate cvtFlat and cvtFlatAtomic.
Fix CNDMASK_B32 definition to have no modifiers.

Review: http://reviews.llvm.org/D17445

Reviewers: tstellarAMD
llvm-svn: 261742
 2016-02-24 14:22:47 +00:00
Artur Pilipenko
5746dd289e NFC. Move isDereferenceable to Loads.h/cpp 
This is a part of the refactoring to unify isSafeToLoadUnconditionally and isDereferenceablePointer functions. In subsequent change I'm going to eliminate isDerferenceableAndAlignedPointer from Loads API, leaving isSafeToLoadSpecualtively the only function to check is load instruction can be speculated.   

Reviewed By: hfinkel

Differential Revision: http://reviews.llvm.org/D16180

llvm-svn: 261736
 2016-02-24 12:49:04 +00:00
Artur Pilipenko
e41e2d4c04 NFC. Move getAlignment helper function from ValueTracking to Value class. 
Reviewed By: reames, hfinkel

Differential Revision: http://reviews.llvm.org/D16144

llvm-svn: 261735
 2016-02-24 12:25:10 +00:00
Nikolay Haustov
0caff3d99c [AMDGPU] fix amd_kernel_code_t bit field position as per spec (added missing reserved fields) 
lit tests passed before and after because it doesn't test the binary representation of amd_kernel_code_t.

Patch by: Valery Pykhtin (Valery.Pykhtin@amd.com)

Reviewers: arsenm
llvm-svn: 261732
 2016-02-24 10:54:25 +00:00
David Majnemer
f4887d90a6 [SimplifyCFG] Do not blindly remove unreachable blocks 
DeleteDeadBlock was called indiscriminately, leading to cleanuprets with
undef cleanuppad references.

Instead, try to drain the BB of most of it's instructions if it is
unreachable.  We can then remove the BB if it solely consists of a
terminator (and maybe some phis).

llvm-svn: 261731
 2016-02-24 10:02:16 +00:00
David Majnemer
83f0a59a00 [CodeView] Describe variables live in x87 registers 
We didn't have a mapping from LLVM's x87 floating point registers to
CodeView's encoding.

llvm-svn: 261730
 2016-02-24 10:01:24 +00:00
Simon Pilgrim
962ee76b8b [X86][SSE] Don't get target shuffle operands prematurely. 
PerformShuffleCombine should be usable by unary and binary target shuffles, but was attempting to get the first two operands whatever the instruction type. Since these are only used for VECTOR_SHUFFLE instructions for one particular combine I've moved them inside the relevant if statement.

llvm-svn: 261727
 2016-02-24 09:07:47 +00:00
Michael Zuckerman
d1c409a5af [LLVM][AVX512][PSHUFHW ][PSHUFLW ] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17538

llvm-svn: 261725
 2016-02-24 08:39:05 +00:00
Igor Breger
8b9daa338d AVX512: Add vpmovzxbw/d/q ,vpmovzxw/d/q ,vpmovzxbdq lowering patterns that support 256bit inputs like AVX patterns ( that are disable in case HasVLX , see SS41I_pmovx_avx2_patterns). 
Differential Revision: http://reviews.llvm.org/D17504

llvm-svn: 261724
 2016-02-24 08:15:20 +00:00
Justin Bogner
c26c003b44 X86: Wrap a helper for an assert in #ifndef NDEBUG 
This function is used in exactly one place, and only in asserts
builds. Move it a few lines up before the use and only define it when
asserts are enabled. Fixes the release build under -Werror.

Also remove the forward declaration and commentary that was basically
identical to the code itself.

llvm-svn: 261722
 2016-02-24 07:58:02 +00:00
Matt Arsenault
6c6bd4573e AMDGPU: Check cheaper condition before SignBitIsZero 
Don't do an expensive computeKnownBits call when we
can do the cheap check for legal offsets first.

llvm-svn: 261720
 2016-02-24 04:55:29 +00:00
Sanjay Patel
4f966611aa [InstCombine] refactor visitOr() to use foldCastedBitwiseLogic() 
Note: The 'and' case in foldCastedBitwiseLogic() is inheriting one extra
check from the nearly identical 'or' case:
  if ((!isa<ICmpInst>(Cast0Src) || !isa<ICmpInst>(Cast1Src))

But I'm not sure how to expose that difference in a regression test. 
Without that check, the 'or' path will infinite loop on:
test/Transforms/InstCombine/zext-or-icmp.ll
because the zext-or-icmp fold is attempting a reverse transform.

The refactoring should extend to the 'xor' case next to solve part of
PR26702.

llvm-svn: 261707
 2016-02-23 23:56:23 +00:00
Derek Schuff
c81038d2b7 Revert "[WebAssembly] Stackify code emitted by eliminateFrameIndex" 
This reverts r261685 due to wasm test breakage.

llvm-svn: 261702
 2016-02-23 22:13:21 +00:00
Tim Northover
9ff0bb755b AArch64: rename compact unwind forms back to UNWIND_ARM64_*. NFC. 
Looks like the global rename last year was a bit over-zealous. These things
really are referred to with ARM64 elsewhere (ld64, libunwind, ...).

llvm-svn: 261698
 2016-02-23 21:49:05 +00:00
Derek Schuff
74080913f6 [WebAssembly] Stackify code emitted by eliminateFrameIndex 
llvm-svn: 261685
 2016-02-23 21:25:17 +00:00
Tim Northover
ccd1c20321 ARM: fix handling of movw/movt relocations with addend. 
We were emitting only one half of a the paired relocations needed for these
instructions because we decided that an offset needed a scattered relocation.
In fact, movw/movt relocations can be paired without being scattered.

llvm-svn: 261679
 2016-02-23 20:20:23 +00:00
Geoff Berry
5377924081 [AArch64] Generate csinv instruction more often 
Reviewers: t.p.northover, jmolloy

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D17546

llvm-svn: 261675
 2016-02-23 19:34:13 +00:00
Hans Wennborg
1c98857e6a Revert r261633 "Supporting all entities declared in lexical scope in LLVM debug info." 
This and the corresponding Clang change caused PR26715.

llvm-svn: 261671
 2016-02-23 19:17:03 +00:00
Davide Italiano
715c1d0a06 [X86ISelLowering] Stop typing the same return over and over and over. 
llvm-svn: 261666
 2016-02-23 18:39:38 +00:00
Weiming Zhao
df8f1f1370 Fix PR25339: ARM Constant Island 
Summary:
Currently, the ARM Constant Island may not converge (or not converge quickly).
This patch let it move to the closest water after the user if it doesn't converge after 15 iterations.

This address https://llvm.org/bugs/show_bug.cgi?id=25339

Reviewers: t.p.northover, srhines, kristof.beyls, aadg, rengolin

Subscribers: weimingz, aemerson, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D16890

llvm-svn: 261665
 2016-02-23 18:39:19 +00:00
Derek Schuff
313b544b12 [WebAssembly] Add TODO comment to revisit red zone size 
llvm-svn: 261664
 2016-02-23 18:17:46 +00:00
Derek Schuff
7fa1e4425f [WebAssembly] Implement red zone for user stack 
Implements a mostly-conventional redzone for the userspace
stack. Because we have unsigned load/store offsets we continue to use a
local SP subtracted from the incoming SP but do not write it back to
memory.

Differential Revision: http://reviews.llvm.org/D17525

llvm-svn: 261662
 2016-02-23 18:13:07 +00:00
Sanjay Patel
e4ec3d519e [InstCombine] improve readability ; NFCI 
Less indenting, named local variables, more descriptive names.

llvm-svn: 261659
 2016-02-23 17:41:34 +00:00
David Majnemer
29ae1c3d76 [WinEH] Don't inline an 'unwinds to caller' cleanupret into funclets which locally unwind 
It is problematic if the inlinee has a cleanupret which unwinds to
caller and we inline it into a call site which doesn't unwind.

If the funclet unwinds anywhere other than to the caller,
then we will give the funclet two unwind destinations.
This will result in a verifier failure.

Seeing as how the caller wasn't an invoke (which would locally unwind)
and that the funclet cannot unwind to caller, we must conclude that an
'unwind to caller' cleanupret is dynamically unreachable.

This fixes PR26698.

Differential Revision: http://reviews.llvm.org/D17536

llvm-svn: 261656
 2016-02-23 17:11:04 +00:00
Sanjay Patel
4e682fcfe8 [InstCombine] less indenting; NFC 
llvm-svn: 261652
 2016-02-23 16:59:21 +00:00
Geoff Berry
a37df81842 [AArch64] Fix fastcc -tailcallopt epilog code generation. 
Summary:
Fix a bug in epilog generation where the incoming stack arguments were
not being popped for fastcc functions when -tailcallopt was passed.

Reviewers: t.p.northover, mcrosier, jmolloy, rengolin

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D16894

llvm-svn: 261650
 2016-02-23 16:54:36 +00:00
Sanjay Patel
70dd21aa9d [InstCombine] add helper function to foldCastedBitwiseLogic() ; NFCI 
This is a straight cut and paste of the existing code and is intended to
be the first step in solving part of PR26702:
https://llvm.org/bugs/show_bug.cgi?id=26702

We should be able to reuse most of this and delete the nearly identical 
existing code in visitOr(). Then, we can enhance visitXor() to use the
same code too.

llvm-svn: 261649
 2016-02-23 16:36:07 +00:00
Aaron Ballman
96f0a702b2 Silencing a signed vs unsigned mismatch. 
llvm-svn: 261640
 2016-02-23 15:02:43 +00:00
Chad Rosier
9d95aa7f78 [AArch64] Fix comment typo in Cyclone scheduling defs. NFC. 
llvm-svn: 261637
 2016-02-23 14:05:13 +00:00
Amjad Aboud
5e45ef3cfb Supporting all entities declared in lexical scope in LLVM debug info. 
Differential Revision: http://reviews.llvm.org/D15976

llvm-svn: 261633
 2016-02-23 13:36:51 +00:00
Chandler Carruth
2b87d730fb [PM] Remove an overly aggressive assert now that I can actually test the 
pattern that triggers it. This essentially requires an immutable
function analysis, as that will survive anything we do to invalidate it.
When we have such patterns, the function analysis manager will not get
cleared between runs of the proxy.

If we actually need an assert about how things are queried, we can add
more elaborate machinery for computing it, but so far I'm not aware of
significant value provided.

Thanks to Justin Lebar for noticing this when he made a (seemingly
innocuous) change to FunctionAttrs that is enough to trigger it in one
test there. Now it is covered by a direct test of the pass manager code.

llvm-svn: 261627
 2016-02-23 10:47:57 +00:00
Junmo Park
90235fdff5 [ARM] fix initialization of PredictableSelectIsExpensive 
Summary:
If we want classify OoO or not, using getSchedModel().isOutOfOrder()
could be more proper way than using Subtarget->isLikeA9().

Reviewers: jmolloy, rengolin

Differential Revision: http://reviews.llvm.org/D17433

llvm-svn: 261623
 2016-02-23 09:56:58 +00:00
Nikolay Haustov
f7d5b41b7c [AMDGPU] Fix operands of S_BFE_U64 and S_BFM_B64 
src1 of s_bfe_u64 is 32-bit (same as s_bfe_i64).
src0 and src1 of s_bfm_b64 are 32-bit.
Update tests.

Review: http://reviews.llvm.org/D17480

Reviewers: arsenm
llvm-svn: 261621
 2016-02-23 09:19:14 +00:00
Igor Breger
e60efa9c40 AVX512: Fix predicate of AVX pcmpeqw/b , pcmpgtb/w/d instructions . AVX512 version of this instructions return result in kmask register, so AVX patterns should not be disabled. 
Differential Revision: http://reviews.llvm.org/D17517

llvm-svn: 261619
 2016-02-23 08:55:33 +00:00
David Majnemer
70ff357751 [WinEH] Visit 'unwind to caller' catchswitches nested in catchswitches 
We had the right logic for the nested cleanuppad case but omitted it for
catchswitches.

llvm-svn: 261615
 2016-02-23 07:18:15 +00:00
Yaron Keren
672ca3153a Assert when trying to seek un-seekable raw_fd_ostream. 
llvm-svn: 261614
 2016-02-23 07:17:58 +00:00
Dehao Chen
ba3eb3f3a0 Add prefix based function layout when profile is available. 
Summary: If a function is hot, put it in text.hot section.

Reviewers: davidxl

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D17532

llvm-svn: 261607
 2016-02-23 03:39:24 +00:00
Duncan P. N. Exon Smith
53cb4596f6 CodeGen: TII: Take MachineInstr& in predicate API, NFC 
Change TargetInstrInfo API to take `MachineInstr&` instead of
`MachineInstr*` in the functions related to predicated instructions
(I'll try to come back later and get some of the rest).  All of these
functions require non-null parameters already, so references are more
clear.  As a bonus, this happens to factor away a host of implicit
iterator => pointer conversions.

No functionality change intended.

llvm-svn: 261605
 2016-02-23 02:46:52 +00:00
Duncan P. N. Exon Smith
dbf1a64537 Revert "Add prefix based function layout when profile is available." 
This reverts commit r261582, since this bot has been broken for four
hours:
http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental_check/19399/

llvm-svn: 261604
 2016-02-23 02:28:40 +00:00
Michael Zolotukhin
7219052084 Follow up for r261597: Add the * to the auto. 
llvm-svn: 261600
 2016-02-23 00:57:48 +00:00
Michael Zolotukhin
3da31c17bb Follow-up for r261595: use range loop. 
llvm-svn: 261597
 2016-02-23 00:48:44 +00:00
Michael Zolotukhin
cb26e1de36 [LoopUnroll] Avoid unnecessary DT recomputation. 
Summary:
When we completely unroll a loop, it's pretty easy to update DT in-place and
thus avoid rebuilding it. DT recalculation is one of the most time-consuming
tasks in loop-unroll, so avoiding it at least in case of full unroll should be
beneficial.

On some extreme (but still real-world) tests this patch improves compile time by
~2x.

Reviewers: escha, jmolloy, hfinkel, sanjoy, chandlerc

Subscribers: joker.eph, sanjoy, llvm-commits

Differential Revision: http://reviews.llvm.org/D17473

llvm-svn: 261595
 2016-02-23 00:30:50 +00:00
Chandler Carruth
37c3c56afb [PM] Improve the API and comments around the analysis manager proxies. 
These are really handles that ensure the analyses get cleared at
appropriate places, and as such copying doesn't really make sense.
Instead, they should look more like unique ownership objects. Make that
the case.

Relatedly, if you create a temporary of one and move out of it
its destructor shouldn't actually clear anything. I don't think there is
any code that can trigger this currently, but it seems like a more
robust implementation.

If folks want, I can add a unittest that forces this to be exercised,
but that seems somewhat pointless -- whether a temporary is ever created
in the innards of AnalysisManager is not really something we should be
adding a reliance on, but I didn't want to leave a timebomb in the code
here.

If anyone has a cleaner way to represent this, I'm all ears, but
I wanted to assure myself that this wasn't in fact responsible for
another bug I'm chasing down (it wasn't) and figured I'd commit that.

llvm-svn: 261594
 2016-02-23 00:05:00 +00:00
Krzysztof Parzyszek
5090bc6ee3 More detailed dependence test between volatile and non-volatile accesses 
Differential Revision: http://reviews.llvm.org/D16857

llvm-svn: 261589
 2016-02-22 23:07:43 +00:00
Dehao Chen
f09ab5a032 Include ProfileData as CodeGen's required library. 
Summary: Fixing buildbot failure introduced by http://reviews.llvm.org/D17460

Reviewers: davidxl, hans

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D17524

llvm-svn: 261588
 2016-02-22 22:54:14 +00:00
Dehao Chen
755e933005 Set function entry count as 0 if sample profile is not found for the function. 
Summary: This change makes the sample profile's behavior consistent with instr profile.

Reviewers: davidxl, eraman, dnovillo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D17522

llvm-svn: 261587
 2016-02-22 22:46:21 +00:00
David Majnemer
f566971993 [X86] Create mergeable constant pool entries for AVX 
We supported creating mergeable constant pool entries for smaller
constants but not for 32-byte AVX constants.

llvm-svn: 261584
 2016-02-22 22:23:11 +00:00
Dehao Chen
b86da71790 Add prefix based function layout when profile is available. 
Summary: If a function is hot, put it in text.hot section.

Reviewers: davidxl

Subscribers: eraman, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D17460

llvm-svn: 261582
 2016-02-22 22:14:14 +00:00
Matt Arsenault
8fecbc9fea SelectionDAG: Use correct addrspace when lowering memcpy 
This was causing assertions later from using the wrong pointer
size with LDS operations. getOptimalMemOpType should also have
address space arguments later.

This avoids assertions in existing tests exposed by
a future commit.

llvm-svn: 261580
 2016-02-22 22:01:42 +00:00
Derek Schuff
5fd7c2542e [WebAssembly] Fix writeback of stack pointer with dynamic alloca 
Previously the stack pointer was only written back to memory in the
prolog. But this is wrong for dynamic allocas, for which
target-independent codegen handles SP updates after the prolog (and
possibly even in another BB). Instead update the SP global in
ADJCALLSTACKDOWN which is generated after the SP update sequence.
This will have further refinements when we add red zone support.

llvm-svn: 261579
 2016-02-22 21:57:17 +00:00
Adam Nemet
6f1d2a2687 [LoopDataPrefetch] Make it testable with opt 
Summary:
Since this is an IR pass it's nice to be able to write tests without
llc.  This is the counterpart of the llc test under
CodeGen/PowerPC/loop-data-prefetch.ll.

Reviewers: hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D17464

llvm-svn: 261578
 2016-02-22 21:41:22 +00:00
Duncan P. N. Exon Smith
429a618d84 CodeGen: Bring back MachineBasicBlock::iterator::getInstrIterator()... 
This is a little embarrassing.

When I reverted r261504 (getIterator() => getInstrIterator()) in
r261567, I did a `git grep` to see if there were new calls to
`getInstrIterator()` that I needed to migrate.  There were 10-20 hits,
and I blindly did a `sed ...` before calling `ninja check`.

However, these were `MachineInstrBundleIterator::getInstrIterator()`,
which predated r261567.  Perhaps coincidentally, these had an identical
name and return type.

This commit undoes my careless sed and restores
`MachineBasicBlock::iterator::getInstrIterator()`.

llvm-svn: 261577
 2016-02-22 21:30:15 +00:00
Michael Zolotukhin
369872c96c [LoopUnrolling] Fix a bug introduced in r259869 (PR26688). 
The issue was that we only required LCSSA rebuilding if the immediate
parent-loop had values used outside of it. The fix is to enaable the
same logic for all outer loops, not only immediate parent.

llvm-svn: 261575
 2016-02-22 21:21:45 +00:00
Davide Italiano
f2c3cb292f [X86ISelLowering] Consolidate duplicated code in a single place. 
llvm-svn: 261573
 2016-02-22 21:06:46 +00:00
Matt Arsenault
34ccf25c19 AMDGPU/R600: Implement allowsMisalignedMemoryAccess 
This avoids some test regressions in a future commit
when unaligned operations are expanded when they
have custom lowering.

llvm-svn: 261570
 2016-02-22 21:04:16 +00:00
Philip Reames
f10b87b138 [RS4GC] "Constant fold" the rs4gc-split-vector-values flag 
This flag was part of a migration to a new means of handling vectors-of-points which was described in the llvm-dev thread "FYI: Relocating vector of pointers".  The old code path has been off by default for a while without complaints, so time to cleanup.

llvm-svn: 261569
 2016-02-22 21:01:28 +00:00
Tim Northover
369e0e389f ARM: sink atomic release barrier as far as possible into cmpxchg. 
DMB instructions can be expensive, so it's best to avoid them if possible. In
atomicrmw operations there will always be an attempted store so a release
barrier is always needed, but in the cmpxchg case we can delay the DMB until we
know we'll definitely try to perform a store (and so need release semantics).

In the strong cmpxchg case this isn't quite free: we must duplicate the LDREX
instructions to skip the barrier on subsequent iterations. The basic outline
becomes:

        ldrex rOld, [rAddr]
        cmp rOld, rDesired
        bne Ldone
        dmb
    Lloop:
        strex rRes, rNew, [rAddr]
        cbz rRes Ldone
        ldrex rOld, [rAddr]
        cmp rOld, rDesired
        beq Lloop
    Ldone:

So we'll skip this version for strong operations in "minsize" functions.

llvm-svn: 261568
 2016-02-22 20:55:50 +00:00
Duncan P. N. Exon Smith
0fa6439bcd Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC" 
This reverts commit r261504, since it's not obvious the new name is
better:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160222/334298.html

I'll recommit if we get consensus that it's the right direction.

llvm-svn: 261567
 2016-02-22 20:49:58 +00:00
Dan Gohman
eb0777680f [WebAssembly] Re-enable the TailDuplicate pass. 
llvm-svn: 261566
 2016-02-22 20:47:12 +00:00
Philip Reames
7715e0d9b9 [RS4GC] Revert optimization attempt due to memory corruption 
This change reverts "246133 [RewriteStatepointsForGC] Reduce the number of new instructions for base pointers" and a follow on bugfix 12575.

As pointed out in pr25846, this code suffers from a memory corruption bug.  Since I'm (empirically) not going to get back to this any time soon, simply reverting the problematic change is the right answer.

llvm-svn: 261565
 2016-02-22 20:45:56 +00:00
JF Bastien
f05f3f0c3e WebAssembly: update expected failures 
clang r261557 lowers va_arg in clang.

llvm-svn: 261564
 2016-02-22 20:37:34 +00:00
Dan Gohman
c71fd3c15c [WebAssembly] Teach address folding to fold bitwise-or nodes. 
LLVM converts adds into ors when it can prove that the operands don't share
any non-zero bits. Teach address folding to recognize or instructions with
constant operands with this property that can be folded into addresses as
if they were adds.

llvm-svn: 261562
 2016-02-22 20:04:02 +00:00
Tom Stellard
d6c924b960 [AMDGPU][llvm-mc] Support for 32-bit inline literals 
Patch by: Artem Tamazov

Summary:
Note: Support for 64-bit inline literals TBD
Added: Support of abs/neg modifiers for literals (incomplete; parsing TBD).
Added: Some TODO comments.
Reworked/clarity: rename isInlineImm() to isInlinableImm()
Reworked/robustness: disallow BitsToFloat() with undefined value in isInlinableImm()
Reworked/reuse: isSSrc32/64(), isVSrc32/64()
Tests added.

Reviewers: tstellarAMD, arsenm

Subscribers: vpykhtin, nhaustov, SamWot, arsenm

Projects: #llvm-amdgpu-spb

Differential Revision: http://reviews.llvm.org/D17204

llvm-svn: 261559
 2016-02-22 19:17:56 +00:00
Tom Stellard
5186536b5b [AMDGPU] [llvm-mc] [VI] Fix encoding of LDS/GDS instructions. 
Patch by: Artem Tamazov

Summary: Tests added.

Reviewers: tstellarAMD, arsenm

Subscribers: vpykhtin, SamWot, #llvm-amdgpu-spb

Projects: #llvm-amdgpu-spb

Differential Revision: http://reviews.llvm.org/D17271

llvm-svn: 261558
 2016-02-22 19:17:53 +00:00
Justin Lebar
f84464712c Revert "[attrs] Handle convergent CallSites." 
This reverts r261544, which was causing a test failure in
Transforms/FunctionAttrs/readattrs.ll.

llvm-svn: 261549
 2016-02-22 18:24:43 +00:00
Justin Lebar
5bee0dc502 Revert "[ifcnv] Add comment explaining why it's OK to duplicate convergent MIs in ifcnv." 
This reverts r261543.  Accidental commit (not LGTM'ed).

llvm-svn: 261547
 2016-02-22 18:17:27 +00:00
Nemanja Ivanovic
662ab414aa Fix for PR26690 take 2 
This is what was meant to be in the initial commit to fix this bug. The
parens were missing. This commit also adds a test case for the bug and
has undergone full testing on PPC and X86.

llvm-svn: 261546
 2016-02-22 18:04:00 +00:00
Justin Lebar
ca379cda9f [attrs] Handle convergent CallSites. 
Summary:
Previously we had a notion of convergent functions but not of convergent
calls.  This is insufficient to correctly analyze calls where the target
is unknown, e.g. indirect calls.

Now a call is convergent if it targets a known-convergent function, or
if it's explicitly marked as convergent.  As usual, we can remove
convergent where we can prove that no convergent operations are
performed in the call.

Reviewers: chandlerc, jingyue

Subscribers: hfinkel, jhen, tra, llvm-commits

Differential Revision: http://reviews.llvm.org/D17317

llvm-svn: 261544
 2016-02-22 17:51:35 +00:00
Justin Lebar
5a4cdf2207 [ifcnv] Add comment explaining why it's OK to duplicate convergent MIs in ifcnv. 
Summary:
Also add a comment briefly explaining what ifcnv is.

No functional changes.

Reviewers: resistor

Subscribers: echristo, tra, llvm-commits

Differential Revision: http://reviews.llvm.org/D17430

llvm-svn: 261543
 2016-02-22 17:51:30 +00:00
Justin Lebar
4e79c03dad [ifcnv] Use unique_ptr in IfConversion. NFC 
Reviewers: rnk

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D17466

llvm-svn: 261541
 2016-02-22 17:51:28 +00:00
Justin Lebar
3251647c03 Don't tail-duplicate blocks that contain convergent instructions. 
Summary:
Convergent instrs shouldn't be made control-dependent on other values,
but this is basically the whole point of tail duplication.  So just bail
if we see a convergent instruction.

Reviewers: iteratee

Subscribers: jholewinski, jhen, hfinkel, tra, jingyue, llvm-commits

Differential Revision: http://reviews.llvm.org/D17320

llvm-svn: 261540
 2016-02-22 17:50:52 +00:00
Dan Gohman
6cd6f419ab [WebAssembly] Properly ignore llvm.dbg.value instructions. 
llvm-svn: 261538
 2016-02-22 17:45:20 +00:00
Sanjoy Das
47bea86903 [ConstantRange] Rename a method and add more doc 
Rename makeNoWrapRegion to a more obvious makeGuaranteedNoWrapRegion,
and add a comment about the counter-intuitive aspects of the function.
This is to help prevent cases like PR26628.

llvm-svn: 261532
 2016-02-22 16:13:02 +00:00
Zoran Jovanovic
8ae69ab849 [mips] added support for trunc macro 
Author: obucina
Reviewers: dsanders
Differential Revision: http://reviews.llvm.org/D15745

llvm-svn: 261529
 2016-02-22 16:00:23 +00:00
Nemanja Ivanovic
752e2bfba7 Revert bad fix for PR26690. 
llvm-svn: 261527
 2016-02-22 15:06:32 +00:00
Nemanja Ivanovic
b136ac47cd Fix for PR26690 
I mistook BitVector::empty() to mean BitVector::count() == 0 and it does
not. Corrected the issue with the fix for PR26500.

llvm-svn: 261525
 2016-02-22 14:47:49 +00:00
Benjamin Kramer
e5027dce2c Fix some abuse of auto flagged by clang's -Wrange-loop-analysis. 
llvm-svn: 261524
 2016-02-22 13:11:58 +00:00
Igor Breger
0f4267c518 AVX512F: Add assembler Intel syntax tests for knl, fix minor bugs. 
Differential Revision: http://reviews.llvm.org/D17498

llvm-svn: 261521
 2016-02-22 12:37:41 +00:00
Igor Breger
2d437b4341 AVX512: Fix scalar mem operands. 
Differential Revision: http://reviews.llvm.org/D17500

llvm-svn: 261520
 2016-02-22 11:48:27 +00:00
Elena Demikhovsky
c545950e89 Allow setting MaxRerollIterations above 16 
By Ayal Zaks.

Differential Revision http://reviews.llvm.org/D17258

llvm-svn: 261517
 2016-02-22 09:38:28 +00:00
Craig Topper
37f137f856 [X86] Minor formatting fix. NFC 
llvm-svn: 261515
 2016-02-22 08:00:04 +00:00
Duncan P. N. Exon Smith
3b54098f86 Reapply "CodeGen: Use references in MachineTraceMetrics::Trace, NFC" 
This reverts commit r261510, effectively reapplying r261509.  The
original commit missed a caller in AArch64ConditionalCompares.

Original commit message:

Pass non-null arguments by reference in MachineTraceMetrics::Trace,
simplifying future work to remove implicit iterator => pointer
conversions.

llvm-svn: 261511
 2016-02-22 03:33:28 +00:00
Duncan P. N. Exon Smith
5d1b25325e Revert "CodeGen: Use references in MachineTraceMetrics::Trace, NFC" 
This reverts commit r261509.  I'm not sure how this compiled locally,
but something was out of whack.

llvm-svn: 261510
 2016-02-22 03:12:42 +00:00
Duncan P. N. Exon Smith
3cbb1cb653 CodeGen: Use references in MachineTraceMetrics::Trace, NFC 
Pass non-null arguments by reference in MachineTraceMetrics::Trace,
simplifying future work to remove implicit iterator => pointer
conversions.

llvm-svn: 261509
 2016-02-22 03:07:49 +00:00
Duncan P. N. Exon Smith
c548df4a3a CodeGen: Explicitly convert from iterator to pointer, NFC 
llvm-svn: 261508
 2016-02-22 02:53:42 +00:00
Duncan P. N. Exon Smith
052f6c7bc1 Document assumption in X86FrameLowering::inlineStackProbe() 
Resolve FIXME from r261504.  Apparently bundled instructions are illegal
here:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160215/334146.html

llvm-svn: 261507
 2016-02-22 02:32:35 +00:00
Duncan P. N. Exon Smith
b2dab65ba3 CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC 
Delete MachineInstr::getIterator(), since the term "iterator" is
overloaded when talking about MachineInstr.

- Downcast to ilist_node in iplist::getNextNode() and getPrevNode() so
  that ilist_node::getIterator() is still available.
- Add it back as MachineInstr::getInstrIterator().  This matches the
  naming in MachineBasicBlock.
- Add MachineInstr::getBundleIterator().  This is explicitly called
  "bundle" (not matching MachineBasicBlock) to disintinguish it clearly
  from ilist_node::getIterator().
- Update all calls.  Some of these I switched to `auto` to remove
  boiler-plate, since the new name is clear about the type.

There was one call I updated that looked fishy, but it wasn't clear what
the right answer was.  This was in X86FrameLowering::inlineStackProbe(),
added in r252578 in lib/Target/X86/X86FrameLowering.cpp.  I opted to
leave the behaviour unchanged, but I'll reply to the original commit on
the list in a moment.

llvm-svn: 261504
 2016-02-21 22:58:35 +00:00
Lang Hames
3749d7d9d4 [Orc] Add stack-realignment code to the i386 resolver function. 
The resolver uses the fxsave/fxrstor instructions, which require 16-byte
alignment, to save SSE state to the stack. Since 16-byte alignment can't be
assumed on all OSes (and all i386 OSes share this function) - add code to
automatically bump the alignment to 16-bytes on entry to the function.

llvm-svn: 261503
 2016-02-21 22:50:26 +00:00
Duncan P. N. Exon Smith
d5e432aea7 ADT: Remove == and != comparisons between ilist iterators and pointers 
I missed == and != when I removed implicit conversions between iterators
and pointers in r252380 since they were defined outside ilist_iterator.

Since they depend on getNodePtrUnchecked(), they indirectly rely on UB.
This commit removes all uses of these operators.  (I'll delete the
operators themselves in a separate commit so that it can be easily
reverted if necessary.)

There should be NFC here.

llvm-svn: 261498
 2016-02-21 20:39:50 +00:00
Duncan P. N. Exon Smith
37982bac02 TransformUtils: Avoid getNodePtrUnchecked() in integer division, NFC 
Stop relying on `getNodePtrUnchecked()` being useful on invalid
iterators.  This function is documented to be for internal use only, and
the pointer type will eventually have to change to remove UB from
ilist_iterator.  Instead, check the iterator before it has been
invalidated.

llvm-svn: 261497
 2016-02-21 20:14:29 +00:00
Duncan P. N. Exon Smith
9a2563de7c ADT: Stop using getNodePtrUnchecked on end() iterators 
Stop using `getNodePtrUnchecked()` when building IR.  Eventually a
dereference will be required to get at the downcast node, since the
iterator will only store an `ilist_node_base` of some sort.

This should have no functionality change for now, but is a path towards
removing some more UB from ilist.

llvm-svn: 261495
 2016-02-21 19:52:15 +00:00
Craig Topper
f1ad8f775d [X86] Remove unused encoding types from disassembler. NFC 
llvm-svn: 261494
 2016-02-21 19:49:16 +00:00
Duncan P. N. Exon Smith
1eee6063b4 CodeGen: Avoid getNodePtrUnchecked() where we need a Value, NFC 
`ilist_iterator<NodeTy>::getNodePtrUnchecked()` is documented as being
for internal use only, but CodeGenPrepare was using it anyway.  This
code relies on pulling out the `Value*` pointer even after the lifetime
of the iterator is over.  But having this pointer available in
ilist_iterator depends on UB in the first place.

Instead, safely pull out the `Value*` when the iterator is alive and
stop using the internal-only API.

There should be no functionality change here.

llvm-svn: 261493
 2016-02-21 19:37:45 +00:00
Simon Pilgrim
ec0f8ea81f [X86][AVX] Add shuffle masking support for EltsFromConsecutiveLoads 
Add support for the case where we have a consecutive load (which must include the first + last elements) with a mixture of undef/zero elements. We load the vector and then apply a shuffle to clear the zero'd elements.

Differential Revision: http://reviews.llvm.org/D17297

llvm-svn: 261490
 2016-02-21 19:15:48 +00:00
Tobias Grosser
7157394614 ScalerEvolution: Only erase temporary values if they actually have been added 
This addresses post-review comments from Sanjoy Das for r261485.

llvm-svn: 261486
 2016-02-21 18:50:09 +00:00
Tobias Grosser
e896bbb2c0 ScalarEvolution: Do not keep temporary PHI values in ValueExprMap 
Before this patch simplified SCEV expressions for PHI nodes were only returned
the very first time getSCEV() was called, but later calls to getSCEV always
returned the non-simplified value, which had "temporarily" been stored in the
ValueExprMap, but was never removed and consequently blocked the caching of the
simplified PHI expression.

llvm-svn: 261485
 2016-02-21 17:42:10 +00:00
Sanjay Patel
ff9ee24191 fix inaccurate comment; NFC 
llvm-svn: 261484
 2016-02-21 17:33:31 +00:00
Sanjay Patel
67805931c5 [InstCombine] add getNegativeIsTrueBoolVec() helper function; NFC 
Originally part of:
http://reviews.llvm.org/D17485

We need this when simplifying masked memory ops too.

llvm-svn: 261483
 2016-02-21 17:29:33 +00:00
Sanjoy Das
7fe777fc31 Fix LLVM's handling and detection of skylake and cannonlake CPUs 
Summary:
 - Rename `"skylake"` == SkylakeServerProc to `"skylake-avx512"`
 - Change `"skylake"` to denote SkylakeClientProc
 - Fix the detection of cpu family 6 and model 94 to be
   SkylakeClientProc instead of SkylakeServerProc
 - Remove the `"cnl"` for CannonLake

Reviewers: craig.topper, delena

Subscribers: zansari, echristo, qcolombet, RKSimon, spatel, DavidKreitzer, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D17090

llvm-svn: 261482
 2016-02-21 17:12:03 +00:00
Sanjoy Das
1d32ffd382 [LoopDeletion] Add an assert that verifies LCSSA 
This is inspired by PR24804 -- had this assert been there before,
isolating the root cause for PR24804 would have been far easier.

llvm-svn: 261481
 2016-02-21 17:11:59 +00:00
JF Bastien
d168b044b1 WebAssembly: update expected torture test failures 
r261457 handles CopyToReg nodes with flag results in LowerCopyToReg, which was causing the SelectionDAGNodes assert.

llvm-svn: 261479
 2016-02-21 16:52:00 +00:00
Dan Gohman
c3f23ceef3 [WebAssembly] Support physical registers in the rewrite-to-discard optimization. 
llvm-svn: 261465
 2016-02-21 03:27:22 +00:00
Duncan P. N. Exon Smith
0d6cf7b3fa IR: Add ConstantData, for operand-less Constants 
Add a common parent `ConstantData` to the constants that have no
operands.  These are guaranteed to represent abstract data that is in no
way tied to a specific Module.

This is a good cleanup on its own.  It also makes it simpler to disallow
RAUW (and factor away use-lists) on these constants in the future.  (I
have some experimental patches that make RAUW illegal on ConstantData,
and they seem to catch a bunch of bugs...)

llvm-svn: 261464
 2016-02-21 02:39:49 +00:00
David Majnemer
b56105ad7f Unbreak non-X86 targets from fallout caused by r261462 
llvm-svn: 261463
 2016-02-21 01:40:04 +00:00
David Majnemer
174ea5bfc4 [X86] Use the correct alignment for COMDAT constant pool entries 
COFF doesn't have sections with mergeable contents.  Instead, each
constant pool entry ends up in a COMDAT section.  The linker, when
choosing between COMDAT sections, doesn't choose the max alignment of
the two sections.  You just get whatever alignment was on the section.

If one constant needed a higher alignment in one object file from
another one, then we will get into trouble if the linker chooses the
lower alignment one.

Instead, lets promote the alignment of the constant pool entry to make
sure we don't use an under aligned constant with an instruction which
assumed otherwise.

This fixes PR26680.

llvm-svn: 261462
 2016-02-21 01:30:30 +00:00
Simon Pilgrim
f781386f81 [InstCombine] SSE/SSE2 (u)comiss/(u)comisd comparison intrinsics only use the lowest vector element 
llvm-svn: 261460
 2016-02-20 23:17:35 +00:00
Dan Gohman
9d09f603ef [WebAssembly] Refine a README.txt entry. 
The register coloring pass may also need to be involved in order to
optimally sort registers.

llvm-svn: 261458
 2016-02-20 23:11:14 +00:00
Dan Gohman
3f10ef519d [WebAssembly] Handle CopyToReg nodes with flag results in LowerCopyToReg. 
llvm-svn: 261457
 2016-02-20 23:09:44 +00:00
Derek Schuff
ee2bcbc1d2 [WebAssembly] Write stack pointer back to memory when FP is used 
The stack pointer is bumped when there is a frame pointer or when there
are static-size objects, but was only getting written back when there
were static-size objects.

llvm-svn: 261453
 2016-02-20 22:18:47 +00:00
Derek Schuff
5cc4608440 [WebAssembly] Stackify function prologs and epilogs 
The instructions are the same, but fewer locals are used.

Differential Revision: http://reviews.llvm.org/D17428

llvm-svn: 261452
 2016-02-20 21:46:50 +00:00
Dan Gohman
86b91ec3dc Don't scan for SSA register operands to update when not in SSA form. 
TailDuplicate can run on either on SSA code or non-SSA code, as indicated to
it by MRI->isSSA() ("PreRegAlloc" here). TailDuplicate does extra work to
preserve SSA invariants when it duplicates code. This patch makes it skip
some of this extra work in the case where the code is not in SSA form.

llvm-svn: 261450
 2016-02-20 21:28:18 +00:00
Nemanja Ivanovic
6ba5cb86b8 Fix the build bot break caused by rL261441. 
The patch has a necessary call to a function inside an assert. Which is fine
when you have asserts turned on. Not so much when they're off. Sorry about
the regression.

llvm-svn: 261447
 2016-02-20 20:45:37 +00:00
Nemanja Ivanovic
57bd7dee35 Fix for PR 26500 
This patch corresponds to review:
http://reviews.llvm.org/D17294

It ensures that whatever block we are emitting the prologue/epilogue into, we
have the necessary scratch registers. It takes away the hard-coded register
numbers for use as scratch registers as registers that are guaranteed to be
available in the function prologue/epilogue are not guaranteed to be available
within the function body. Since we shrink-wrap, the prologue/epilogue may end
up in the function body.

llvm-svn: 261441
 2016-02-20 18:16:25 +00:00
Simon Pilgrim
1f327425d2 [DAGCombiner] Use getBitcast helper when possible. NFCI. 
llvm-svn: 261437
 2016-02-20 15:05:29 +00:00
Simon Pilgrim
f7fbbebbc2 [X86][SSE] Fixed issue with commutation of 'faux unary' target shuffles (PR26667) 
Fixed a bug introduced by D16683 when a binary shuffle is simplified to a unary shuffle (with undef/zero sentinel mask indices) - if this resulted in only the second input being used combineX86ShuffleChain failed to take this into account and still referenced the first input.

llvm-svn: 261434
 2016-02-20 14:39:45 +00:00
Simon Pilgrim
3ddb55acee [X86][SSE] Move all undef/zero cases before target shuffle combining. 
First small step towards fixing PR26667 - we need to ensure that combineX86ShuffleChain only gets called with a valid shuffle input node (a similar issue was found in D17041).

llvm-svn: 261433
 2016-02-20 12:57:32 +00:00