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16695 Commits

Author SHA1 Message Date
Bill Wendling
2b53c0830d Initialize HasPOPCNT. 
llvm-svn: 120923
 2010-12-04 23:57:24 +00:00
Benjamin Kramer
851691ddb2 Add patterns for the x86 popcnt instruction. 
- Also adds a new POPCNT subtarget feature that is currently enabled if the target
  supports SSE4.2 (nehalem) or SSE4A (barcelona).

llvm-svn: 120917
 2010-12-04 20:32:23 +00:00
Benjamin Kramer
77faee6ba1 Simplify code. No functionality change. 
llvm-svn: 120907
 2010-12-04 14:22:24 +00:00
Bob Wilson
20c65a9d33 The Thumb tADDrSPi instruction is not valid when the destination is SP. 
Check for that and try narrowing it to tADDspi instead.  Radar 8724703.

llvm-svn: 120892
 2010-12-04 04:40:19 +00:00
Rafael Espindola
9215947c83 There are two reasons why we might want to use 
foo = a - b
.long foo
instead of just
.long a - b

First, on darwin9 64 bits the assembler produces the wrong result. Second,
if "a" is the end of the section all darwin assemblers (9, 10 and mc) will not
consider a - b to be a constant but will if the dummy foo is created.

Split how we handle these cases. The first one is something MC should take care
of. The second one has to be handled by the caller.

llvm-svn: 120889
 2010-12-04 03:21:47 +00:00
Jim Grosbach
4c10ffa7c3 Encode condition code for Thumb1 conditional branch instruction. 
llvm-svn: 120865
 2010-12-04 00:20:40 +00:00
Jim Grosbach
1dac8796d5 Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible. 
tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577

llvm-svn: 120858
 2010-12-03 23:54:18 +00:00
Bill Wendling
7e27f17312 Use correct variable names to match the patterns. 
llvm-svn: 120857
 2010-12-03 23:44:24 +00:00
Jim Grosbach
3b5c857f01 Match pattern operand names to expected encoding field names. This corrects the 
operand encoding ordering of the instruction.

llvm-svn: 120852
 2010-12-03 23:21:25 +00:00
Jim Grosbach
dbefb3e7e5 Remove incorrect BL target encoding (it's similar to, but not the same as the 
ARM instruction). Add encoding of bits 13 and 11.

llvm-svn: 120849
 2010-12-03 22:33:42 +00:00
Jim Grosbach
8cef570ed9 Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order 
halfword being emitted to the stream first. rdar://8728174

llvm-svn: 120848
 2010-12-03 22:31:40 +00:00
Nate Begeman
d4310b6d7c Revert this change since it breaks a couple of the AVX tests. 
I'm unclear if the tests are actually correct or not, but reverting for now.

llvm-svn: 120847
 2010-12-03 22:29:15 +00:00
Nate Begeman
deb26223bd Scalar f32/f64 are also subregs of ymm regs 
llvm-svn: 120844
 2010-12-03 21:54:39 +00:00
Nate Begeman
3911dcfd71 Remove SSE1-4 disable when AVX is enabled. While this may be useful for development, 
it completely breaks scalar fp in xmm regs when AVX is enabled.

llvm-svn: 120843
 2010-12-03 21:54:14 +00:00
Jim Grosbach
c69ad2176a When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the 
32-bit wide version by adding the .w suffix.

llvm-svn: 120838
 2010-12-03 20:33:01 +00:00
Benjamin Kramer
e27eff8888 Remove unused variable. 
llvm-svn: 120836
 2010-12-03 19:55:37 +00:00
Jim Grosbach
c8ce9a3453 Reduce t2 ldr/str instructions to the correct t1 versions when there's an 
immediate offset.

llvm-svn: 120833
 2010-12-03 19:47:11 +00:00
Jason W Kim
27bbab7e31 fix ARM::fixup_arm_branch, cleanup, and share more code between ELF and Darwin 
llvm-svn: 120832
 2010-12-03 19:40:23 +00:00
Jim Grosbach
25da270139 No need to declare EncoderMethod property anymore; just assign to it. 
llvm-svn: 120831
 2010-12-03 19:31:00 +00:00
Jim Grosbach
d0db6c9f0e Add FIXMEs. 
llvm-svn: 120824
 2010-12-03 18:37:17 +00:00
Jim Grosbach
dca34b5da7 Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD. 
llvm-svn: 120822
 2010-12-03 18:31:03 +00:00
Bill Wendling
b7df584ef7 Don't overwrite the opcode passed into the T1Special pattern. 
llvm-svn: 120782
 2010-12-03 02:02:58 +00:00
Bill Wendling
c4858cb4c3 Add Thumb encoding for some more instructions. 
llvm-svn: 120780
 2010-12-03 01:55:47 +00:00
Rafael Espindola
3e119b0bb4 Try to resolve symbol differences early, and if successful create a plain 
data fragment. This reduces the time to assemble the test in 8711 from 60s to
54s.

llvm-svn: 120767
 2010-12-03 00:55:40 +00:00
Bill Wendling
2f6a820abe The tLDR instruction wasn't encoded properly: 
<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>

Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.

llvm-svn: 120766
 2010-12-03 00:53:22 +00:00
Jim Grosbach
0bd3b0fd6c Trailing whitespace. 
llvm-svn: 120748
 2010-12-02 23:05:38 +00:00
Devang Patel
822facd787 Use set directive for StartMinusEndExpr. 
This is a fix for llvm-gcc-i386-darwin9 buildbot failure.

llvm-svn: 120742
 2010-12-02 21:32:30 +00:00
Jim Grosbach
b6d0c8d5b1 When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes, 
not thumb2.

llvm-svn: 120711
 2010-12-02 16:42:25 +00:00
Jim Grosbach
78ef3199c8 Fix copy/pasto in vmin.f32 encoding. 
llvm-svn: 120709
 2010-12-02 16:30:58 +00:00
Wesley Peck
09a4bffe09 Teaching MBlaze backend how to reverse branch conditions. 
llvm-svn: 120707
 2010-12-02 16:17:11 +00:00
Jim Grosbach
0e71db6919 Add support for binary encoding of ARM 'adr' instructions referencing constant 
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.

llvm-svn: 120635
 2010-12-02 00:28:45 +00:00
Devang Patel
409a5ff824 Revert r120580. 
llvm-svn: 120630
 2010-12-02 00:22:29 +00:00
Evan Cheng
4118b24aca Fix and re-enable tail call optimization of expanded libcalls. 
llvm-svn: 120622
 2010-12-01 22:59:46 +00:00
Jason W Kim
7d4b30652e fixing style nit: move class static to global static 
llvm-svn: 120619
 2010-12-01 22:46:50 +00:00
Bill Wendling
d85ff071c0 Add a post encoder method to the VFP instructions to convert them to the Thumb2 
encoding if we're in that mode.

llvm-svn: 120608
 2010-12-01 21:54:50 +00:00
Jim Grosbach
b1b1ff4271 Use the correct fixup type for ARM VLDR* 
llvm-svn: 120604
 2010-12-01 21:09:40 +00:00
Jim Grosbach
b2a12afa5f Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR 
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.

llvm-svn: 120594
 2010-12-01 19:47:31 +00:00
Owen Anderson
8802c68592 Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax. 
llvm-svn: 120589
 2010-12-01 19:18:46 +00:00
Jason W Kim
d468d24fc9 kill trailing space 
llvm-svn: 120586
 2010-12-01 19:07:22 +00:00
Jim Grosbach
25b2b536f3 10 bits, not 12. 
llvm-svn: 120584
 2010-12-01 18:51:32 +00:00
Devang Patel
e68cb5a5cf Disable debug info for x86-darwin9 and earlier until PR 8715 and radar 8709290 are fixed. 
llvm-svn: 120580
 2010-12-01 16:59:34 +00:00
Duncan Sands
cd4f56b8e2 I don't think it makes any sense to assert that the target supports SSE3 here. 
The user (i.e. whoever generated a call to the intrinsic in the first place) is
essentially asking for a particular instruction to be placed in the assembler.
If that instruction won't execute on the target machine, that's their problem
not ours.  Two buildbots with processors that don't support SSE3 were barfing
on the apm.ll test in CodeGen/X86 because of this assertion.

llvm-svn: 120574
 2010-12-01 12:58:13 +00:00
Che-Liang Chiou
c61d8fa0e3 ptx: bug fix: use after free 
llvm-svn: 120571
 2010-12-01 11:45:53 +00:00
Jim Grosbach
a3e6ffffe5 Elaborate on FIXME. 
llvm-svn: 120552
 2010-12-01 04:01:17 +00:00
Jim Grosbach
b2044fcba1 Move the ARMAsmPrinter class defintiion into a header file. 
llvm-svn: 120551
 2010-12-01 03:45:07 +00:00
Evan Cheng
84162760b7 Speculatively disable x86 portion of r120501 to appease the x86_64 buildbot. 
llvm-svn: 120549
 2010-12-01 03:27:20 +00:00
Bill Wendling
e62557dc3c Remove "comparison of integers of different signs" warning by making the 
variable unsigned.

llvm-svn: 120541
 2010-12-01 02:49:04 +00:00
Bill Wendling
4fc1c4ee84 General cleanups of comments. 
llvm-svn: 120536
 2010-12-01 02:42:55 +00:00
Jason W Kim
4d960e071c ARM/MC/ELF relocation "hello world" for movw/movt. 
Lifted adjustFixupValue() from Darwin for sharing w ELF.
Test added
TODO:
  refactor ELFObjectWriter::RecordRelocation more.
  Possibly share more code with Darwin?
  Lots more relocations...

llvm-svn: 120534
 2010-12-01 02:40:06 +00:00
Bill Wendling
b7635b1ed3 Formatting. It's all the rage! 
llvm-svn: 120533
 2010-12-01 02:36:55 +00:00
Bill Wendling
8861fb7484 More refactoring. This time the T1pI pattern. 
llvm-svn: 120532
 2010-12-01 02:28:08 +00:00
Eric Christopher
5f7eeae6ba Refactor load/store handling again. Simplify and make some room for 
reg+reg handling.

llvm-svn: 120526
 2010-12-01 01:40:24 +00:00
Jan Wen Voung
c34fbc5bb1 Initialize an ARMConstantPoolValue field. 
llvm-svn: 120525
 2010-12-01 01:38:58 +00:00
Bill Wendling
ccfea264ff s/T1pIEncode/T1pILdStEncode/g 
s/T1pIEncodeImm/T1pILdStEncodeImm/g

llvm-svn: 120524
 2010-12-01 01:38:08 +00:00
Bill Wendling
517dd72f06 Renaming variables to coincide with documentation. No functionality change. 
llvm-svn: 120522
 2010-12-01 01:32:02 +00:00
Bill Wendling
8ebed2442e Refactor T1sI and T1sIt encodings into helper classes. 
llvm-svn: 120518
 2010-12-01 01:20:15 +00:00
Bill Wendling
60d0e1a06c Refactor the T1sIt encodings into a parent class to get rid of all of the "let" 
statements.

llvm-svn: 120512
 2010-12-01 00:48:44 +00:00
Owen Anderson
2299afbb49 Use by-name rather than by-order matching for NEON operands. 
llvm-svn: 120507
 2010-12-01 00:28:25 +00:00
Evan Cheng
f7e586d749 Enable sibling call optimization of libcalls which are expanded during 
legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777

llvm-svn: 120501
 2010-11-30 23:55:39 +00:00
Bill Wendling
6a48b15c80 Rename operands to match ARM documentation. No functionality change. 
llvm-svn: 120500
 2010-11-30 23:54:45 +00:00
Jim Grosbach
c8c81941f6 Fix typo. 
llvm-svn: 120499
 2010-11-30 23:51:41 +00:00
Jim Grosbach
ce4e8350aa Trailing whitespace. 
llvm-svn: 120497
 2010-11-30 23:29:24 +00:00
Jason W Kim
725321c3c7 Thanks to JimG for catching this! 
llvm-svn: 120494
 2010-11-30 23:27:18 +00:00
Bill Wendling
745e2de9dc Inline classes that were used in only one place. 
llvm-svn: 120488
 2010-11-30 23:16:25 +00:00
Bill Wendling
e85934f8a5 * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as 
t_addrmode_s4, but with a different scaling factor.

* Encode the Thumb1 load and store instructions. This involved a bit of
  refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
  were removed.

llvm-svn: 120482
 2010-11-30 22:57:21 +00:00
Owen Anderson
5aff471eb8 Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the 
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.

llvm-svn: 120481
 2010-11-30 22:45:47 +00:00
Jim Grosbach
09095b4dd9 Fix handling of ARM negative pc-relative fixups for loads and stores. 
llvm-svn: 120480
 2010-11-30 22:40:36 +00:00
Eric Christopher
3a1c712e47 Move X86InstrFPStack.td over to PseudoI as well. 
llvm-svn: 120470
 2010-11-30 21:57:32 +00:00
Eric Christopher
b15c993a73 Migrate X86InstrControl.td to use PseudoI and fix a couple of 80-col violations 
while I'm in there.

llvm-svn: 120466
 2010-11-30 21:37:36 +00:00
Owen Anderson
20a6f2bd2e Provide Thumb2 encodings for a few miscellaneous instructions. 
llvm-svn: 120455
 2010-11-30 20:00:01 +00:00
Jim Grosbach
532d63789b Add FIXME 
llvm-svn: 120451
 2010-11-30 19:25:56 +00:00
Owen Anderson
5f7b3e919b Add encoding support for Thumb2 PLD and PLI instructions. 
llvm-svn: 120449
 2010-11-30 19:19:31 +00:00
Eric Christopher
95f0d1fe65 Noticed this on inspection, fix and update some comments. 
llvm-svn: 120447
 2010-11-30 19:14:07 +00:00
Jim Grosbach
aa96c057be Pseudo-ize ARM MOVPCRX 
llvm-svn: 120442
 2010-11-30 18:56:36 +00:00
Owen Anderson
6581027075 Provide encodings for a few more load/store variants. 
llvm-svn: 120439
 2010-11-30 18:38:28 +00:00
Jim Grosbach
cb8193b99e Pseudo-ize BX_CALL and friends. Remove dead instruction format classes. 
rdar://8685712

llvm-svn: 120438
 2010-11-30 18:30:19 +00:00
Che-Liang Chiou
f594fe5fc5 ptx: add command-line options for gpu target and ptx version 
llvm-svn: 120423
 2010-11-30 10:14:14 +00:00
Eric Christopher
1a99e7ebdb Fix some grammar in comments I noticed. 
llvm-svn: 120416
 2010-11-30 09:11:54 +00:00
Eric Christopher
d8e045d29e This defaults to GenericDomain. 
llvm-svn: 120415
 2010-11-30 09:11:07 +00:00
Eric Christopher
6a21ceab5c Implement a PseudoI class and transfer the sse instructions over to use 
it.

llvm-svn: 120412
 2010-11-30 08:57:23 +00:00
Eric Christopher
73365ae8b6 Fix insertion point in pcmp expander. 
While I'm there, clean up too many \n even for me.

llvm-svn: 120411
 2010-11-30 08:20:21 +00:00
Eric Christopher
2170738538 Fix some cleanups from my last patch. 
llvm-svn: 120410
 2010-11-30 08:10:28 +00:00
Bill Wendling
ae920bcc50 Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost 
certainly be made more generic. But it does allow us to parse something like:

          ldr     r3, [r2, r4]

correctly in Thumb mode.

llvm-svn: 120408
 2010-11-30 07:44:32 +00:00
Che-Liang Chiou
df20cec4fb ptx: add ld instruction 
support register and register-immediate addressing mode

todo: immediate and register-register addressing mode
llvm-svn: 120407
 2010-11-30 07:34:44 +00:00
Eric Christopher
f27f0b5234 Rewrite mwait and monitor support and custom lower arguments. 
Fixes PR8573.

llvm-svn: 120404
 2010-11-30 07:20:12 +00:00
Bill Wendling
a3cc011fc5 Minor cleanups. No functional change. 
llvm-svn: 120372
 2010-11-30 00:50:22 +00:00
Bill Wendling
5030f8359b s/ARM::BRIND/ARM::BX/g to coincide with r120366. 
llvm-svn: 120371
 2010-11-30 00:48:15 +00:00
Bill Wendling
6bcbf9bd7c Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't 
able to match this yet.

llvm-svn: 120369
 2010-11-30 00:34:08 +00:00
Jim Grosbach
6c0221e3ae Rename BX/BRIND/etc patterns to clarify which is actually the BX instruction 
and which are pseudos.

llvm-svn: 120366
 2010-11-30 00:24:05 +00:00
Bill Wendling
7cbe5a236c Add some encoding for the adr instruction. Labels still need to be finished. 
llvm-svn: 120365
 2010-11-30 00:18:30 +00:00
Owen Anderson
b6e1c56c79 Correct Thumb2 encodings for a much wider range of loads and stores. 
llvm-svn: 120364
 2010-11-30 00:14:31 +00:00
Jim Grosbach
5f2a3880a8 Make a few more ARM pseudo instructions actually use the PseudoInst base class. 
llvm-svn: 120362
 2010-11-30 00:09:06 +00:00
Bill Wendling
9859e95ca2 Predicate encoding should be withing {}s. And general cleanup. 
llvm-svn: 120361
 2010-11-30 00:08:20 +00:00
Bill Wendling
6b680b11e8 Predicate encoding should be withing {}s. 
llvm-svn: 120360
 2010-11-30 00:05:25 +00:00
Bob Wilson
f5eece615c Fix the encoding of VLD4-dup alignment. 
The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function.  Use it
for all the VLD-dup instructions for the sake of consistency.

llvm-svn: 120358
 2010-11-30 00:00:42 +00:00
Bob Wilson
1be989686c Rename VLDnDUP instructions with double-spaced registers 
in an attempt to make things a little more consistent.

llvm-svn: 120357
 2010-11-30 00:00:38 +00:00
Bob Wilson
bd3d3d2937 Add support for NEON VLD3-dup instructions. 
The encoding for alignment in VLD4-dup instructions is still a work in progress.

llvm-svn: 120356
 2010-11-30 00:00:35 +00:00
Jim Grosbach
58e4c01d0d Simplify definitions of the ARM eh.sjlj.*jmp pseudo instructions. 
llvm-svn: 120354
 2010-11-29 23:51:31 +00:00
Jim Grosbach
b796df67e9 Parameterize ARMPseudoInst size property. 
llvm-svn: 120353
 2010-11-29 23:48:41 +00:00
Jim Grosbach
81880e96fc Add a few missing initializers. 
llvm-svn: 120350
 2010-11-29 23:41:10 +00:00
Jim Grosbach
4e37703b2c Nuke trailing whitespace. 
llvm-svn: 120344
 2010-11-29 23:18:01 +00:00
Jim Grosbach
d92d1fa9e6 Nuke a FIXME. No need to be fancier here, as ARM handles constant pools 
locations and formatting specially. rdar://7353441

llvm-svn: 120343
 2010-11-29 23:09:20 +00:00
Owen Anderson
14abbb1a2e Provide Thumb2 encodings for basic loads and stores. 
llvm-svn: 120340
 2010-11-29 22:44:32 +00:00
Evan Cheng
78baa6f30d Mark Darwin call instructions as using "r7" to prevent the frame-register 
assignment instructions from being moved below / above calls.
rdar://8690640

llvm-svn: 120339
 2010-11-29 22:43:27 +00:00
Jim Grosbach
90cb1bbd23 Nuke dead isCodeGenOnly annotation and extraneous comment. 
llvm-svn: 120338
 2010-11-29 22:40:58 +00:00
Jim Grosbach
208782384a tidy up. 
llvm-svn: 120335
 2010-11-29 22:38:48 +00:00
Bill Wendling
c2693dcc02 Thumb encodings for conditional moves. 
llvm-svn: 120334
 2010-11-29 22:37:46 +00:00
Jim Grosbach
89e90b7310 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw 
instructions. This simplifies instruction printing and disassembly.

llvm-svn: 120333
 2010-11-29 22:37:40 +00:00
Bill Wendling
15e68b7a35 Refactor some of the "disassembly-only" instructions into a base class. This 
reduces some code duplication.

llvm-svn: 120326
 2010-11-29 22:15:03 +00:00
Eric Christopher
625238ff3e Update fastisel for the changes in r120272. 
llvm-svn: 120324
 2010-11-29 21:56:23 +00:00
Jim Grosbach
71042b51a1 Rename t2 TBB and TBH instructions to reference that they encode the jump table 
data. Next up, pseudo-izing them.

llvm-svn: 120320
 2010-11-29 21:28:32 +00:00
Owen Anderson
4b82810d8c Improving the factoring of several instruction encodings. 
llvm-svn: 120317
 2010-11-29 20:38:48 +00:00
Bob Wilson
aa197b07e6 Add support for NEON VLD3-dup instructions. 
llvm-svn: 120312
 2010-11-29 19:35:29 +00:00
Bob Wilson
cb675664c4 Fix copy-and-paste errors in VLD2-dup scheduling itineraries. 
llvm-svn: 120311
 2010-11-29 19:35:23 +00:00
Jim Grosbach
3e84f9d6cb ARM Pseudo-ize tBR_JTr. 
llvm-svn: 120310
 2010-11-29 19:32:47 +00:00
Owen Anderson
049177ff7f Thumb2 encodings for MSR and MRS. 
llvm-svn: 120309
 2010-11-29 19:29:15 +00:00
Owen Anderson
78d84a1921 Thumb2 encodings for system instructions. 
llvm-svn: 120307
 2010-11-29 19:22:08 +00:00
Owen Anderson
b29182b60f Thumb2 encodings for branches and IT blocks. 
llvm-svn: 120306
 2010-11-29 18:54:38 +00:00
Jim Grosbach
0d235c0c37 The ARM BR_JT* pseudos don't need to use the printer jtblock_operand node to 
get the pretty-printer. That's handled explicityly by the MC lowering now.

llvm-svn: 120305
 2010-11-29 18:53:24 +00:00
Michael J. Spencer
4a63404543 I swear I did a make clean and make before committing all this... 
llvm-svn: 120304
 2010-11-29 18:47:54 +00:00
Jim Grosbach
9e2ed21ad0 Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos. 
llvm-svn: 120303
 2010-11-29 18:37:44 +00:00
Michael J. Spencer
d5ec932c3a Merge System into Support. 
llvm-svn: 120298
 2010-11-29 18:16:10 +00:00
Kalle Raiskila
71dec6ff42 Handle lshr for i128 correctly on SPU also when 
shiftamount > 7.

llvm-svn: 120288
 2010-11-29 14:44:28 +00:00
Kalle Raiskila
45865e9165 Enable PostRA scheduling for SPU. 
This speeds up selected test cases with up to
5% - no slowdowns observed.

llvm-svn: 120286
 2010-11-29 10:30:25 +00:00
Kalle Raiskila
64f85ff7b3 Allow machine LICM to do its job on SPU. 
-return a sensible value for register pressure
-add pattern to 'ila' instrucion

llvm-svn: 120285
 2010-11-29 10:08:09 +00:00
Kalle Raiskila
46d01503cd Add missing i128 case. 
llvm-svn: 120284
 2010-11-29 09:36:26 +00:00
Bill Wendling
c0055893db Add more Thumb encodings. 
llvm-svn: 120279
 2010-11-29 01:07:48 +00:00
Bill Wendling
b54752da15 More Thumb encodings. 
llvm-svn: 120278
 2010-11-29 01:00:43 +00:00
Bill Wendling
8f0b624061 Add Thumb encodings for REV instructions. 
llvm-svn: 120277
 2010-11-29 00:42:50 +00:00
Bill Wendling
d233cab1eb Add more Thumb encodings. 
llvm-svn: 120272
 2010-11-29 00:18:15 +00:00
Rafael Espindola
d5f118a011 Make EmitIntValue non virtual. 
llvm-svn: 120271
 2010-11-28 23:22:44 +00:00
Rafael Espindola
9287c4b38f Move lowering of TLS_addr32 and TLS_addr64 to X86MCInstLower. 
llvm-svn: 120263
 2010-11-28 21:16:39 +00:00
Chris Lattner
a11c5c5c32 fix PR8686, accepting a 'b' suffix at the end of all the setcc 
instructions.  I choose to handle this with an asmparser hack,
though it could be handled by changing all the instruction definitions
to allow be "setneb" instead of "setne".  The asm parser hack is
better in this case, because we want the disassembler to produce
setne, not setneb.

llvm-svn: 120260
 2010-11-28 20:23:50 +00:00
Nicolas Geoffray
9705544e7c When emitting a single function with cppgen=function, you don't want to emit 
initializers of global variables used in the function.
Also make sure to emit the operands of a constant.

llvm-svn: 120253
 2010-11-28 18:00:53 +00:00
Rafael Espindola
38c559954c Move the PTXMCAsmStreamer class to the .cpp file. 
llvm-svn: 120241
 2010-11-28 14:48:34 +00:00
Rafael Espindola
f77005db2b Define generic 1, 2 and 4 byte pc relative relocations. They are common 
and at least the 4 byte one will be needed to implement the .cfi_* directives.

llvm-svn: 120240
 2010-11-28 14:17:56 +00:00
Bob Wilson
3bb61d1932 Add support for NEON VLD2-dup instructions. 
llvm-svn: 120236
 2010-11-28 06:51:26 +00:00
Bob Wilson
f4df482b0d Another minor refactoring for VLD1DUP instructions. 
The op11_8 field is the same for all of them so put it in the instruction
classes instead of specifying it separately for each instruction.

llvm-svn: 120234
 2010-11-28 06:51:15 +00:00
Bob Wilson
edf156f4af Add entry in getTargetNodeName() for ARMISD::VBICIMM. 
llvm-svn: 120233
 2010-11-28 06:51:11 +00:00
Anton Korobeynikov
598465c605 Move more PEI-related hooks to TFI 
llvm-svn: 120229
 2010-11-27 23:05:25 +00:00
Anton Korobeynikov
c87f68e32e Move callee-saved regs spills / reloads to TFI 
llvm-svn: 120228
 2010-11-27 23:05:03 +00:00
Rafael Espindola
45cd9713f2 Lower TLS_addr32 and TLS_addr64. 
llvm-svn: 120225
 2010-11-27 20:43:02 +00:00
Rafael Espindola
6f5680f4a0 Implement the data16 prefix. 
llvm-svn: 120224
 2010-11-27 20:29:45 +00:00
Bob Wilson
3e64f6b309 Refactor. Set alignment bit in VLD1-dup instruction classes. 
llvm-svn: 120197
 2010-11-27 07:12:02 +00:00
Bob Wilson
cbd6281807 Add NEON VLD1-dup instructions (load 1 element to all lanes). 
llvm-svn: 120194
 2010-11-27 06:35:16 +00:00
Bob Wilson
c66e4574f1 Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions. 
I added these instructions recently but I have no idea where these "1"
values in the NextCycles field came from.  As far as I can tell now,
these instruction stages are clearly intended to overlap.

llvm-svn: 120193
 2010-11-27 06:35:09 +00:00
Daniel Dunbar
bcc15fb05d MC/Mach-O: Switch to using MachOFormat.h. 
- I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another).

llvm-svn: 120187
 2010-11-27 04:38:36 +00:00
Rafael Espindola
0641196380 Remove the unused TheTarget member. 
llvm-svn: 120168
 2010-11-26 04:24:21 +00:00
Rafael Espindola
e3dc1c951c Use multiple 0x66 prefixes so that all nops up to 15 bytes are a single instruction. 
llvm-svn: 120147
 2010-11-25 17:14:16 +00:00
Benjamin Kramer
35b0f6e5a6 Namespacify. 
llvm-svn: 120146
 2010-11-25 16:42:51 +00:00