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Commit Graph

107 Commits

Author SHA1 Message Date
Rafael Espindola
a96c205e12 add optional input flag to FMRRD 
llvm-svn: 30774
 2006-10-06 20:33:26 +00:00
Rafael Espindola
54301ca490 add support for calling functions that return double 
llvm-svn: 30771
 2006-10-06 19:10:05 +00:00
Rafael Espindola
d870b158b3 fix some bugs affecting functions with no arguments 
llvm-svn: 30767
 2006-10-06 17:26:30 +00:00
Rafael Espindola
f679bdf121 add support for calling functions that have double arguments 
llvm-svn: 30765
 2006-10-06 12:50:22 +00:00
Evan Cheng
275825195a Make use of getStore(). 
llvm-svn: 30759
 2006-10-05 23:01:46 +00:00
Rafael Espindola
2e4743b6d1 use a const ref for passing the vector to ArgumentLayout 
llvm-svn: 30756
 2006-10-05 17:46:48 +00:00
Rafael Espindola
f0e4950ef4 implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL 
implement FMDRR
add support for f64 function arguments

llvm-svn: 30754
 2006-10-05 16:48:49 +00:00
Rafael Espindola
b77754ce4d Implement floating point constants 
llvm-svn: 30704
 2006-10-03 17:27:58 +00:00
Rafael Espindola
36c3e0028b fix the names of the 64bit fp register 
initial support for returning 64bit floating point numbers

llvm-svn: 30692
 2006-10-02 19:30:56 +00:00
Rafael Espindola
1b39270c95 add floating point registers 
implement SINT_TO_FP

llvm-svn: 30673
 2006-09-29 21:20:16 +00:00
Rafael Espindola
a51ec7153c more condition codes 
llvm-svn: 30567
 2006-09-21 13:06:26 +00:00
Rafael Espindola
4de4f87be5 if a constant can't be an immediate, add it to the constant pool 
llvm-svn: 30566
 2006-09-21 11:29:52 +00:00
Rafael Espindola
1a3020bfcf add shifts to addressing mode 1 
llvm-svn: 30291
 2006-09-13 12:09:43 +00:00
Evan Cheng
dd52a60189 Reflects MachineConstantPoolEntry changes. 
llvm-svn: 30279
 2006-09-12 21:04:05 +00:00
Rafael Espindola
d8b1142d79 add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1 
llvm-svn: 30261
 2006-09-11 19:23:32 +00:00
Rafael Espindola
89ac048c5d partial implementation of the ARM Addressing Mode 1 
llvm-svn: 30252
 2006-09-11 17:25:40 +00:00
Rafael Espindola
de18749e1f add support for returning 64bit values 
llvm-svn: 30103
 2006-09-04 19:05:01 +00:00
Rafael Espindola
65007fc49c add the SETULT condition code 
llvm-svn: 30067
 2006-09-03 13:19:16 +00:00
Rafael Espindola
5c0443c41e add more condition codes 
llvm-svn: 30056
 2006-09-02 20:24:25 +00:00
Evan Cheng
2db7799507 Select() no longer require Result operand by reference. 
llvm-svn: 29898
 2006-08-26 05:34:46 +00:00
Rafael Espindola
91954ae78f use @ for comments 
store LR in an arbitrary stack slot
add support for writing varargs functions

llvm-svn: 29876
 2006-08-25 17:55:16 +00:00
Rafael Espindola
fb63eba81c add the "eq" condition code 
implement a movcond instruction

llvm-svn: 29857
 2006-08-24 17:19:08 +00:00
Rafael Espindola
cf999a6d39 create a generic bcond instruction that has a conditional code argument 
llvm-svn: 29856
 2006-08-24 16:13:15 +00:00
Rafael Espindola
9e2a2dfb2d initial support for branches 
llvm-svn: 29854
 2006-08-24 13:45:55 +00:00
Rafael Espindola
474f6c5bf1 initial support for select 
llvm-svn: 29802
 2006-08-21 22:00:32 +00:00
Rafael Espindola
c255c4c434 call computeRegisterProperties 
llvm-svn: 29780
 2006-08-20 01:49:49 +00:00
Rafael Espindola
ff879761c1 add a "load effective address" 
llvm-svn: 29748
 2006-08-17 17:09:40 +00:00
Rafael Espindola
b98e92cb78 Declare the callee saved regs 
Remove the hard coded store and load of the link register
Implement ARMFrameInfo

llvm-svn: 29727
 2006-08-16 14:43:33 +00:00
Rafael Espindola
48bed9023d select code like 
ldr rx, [ry, #offset]

llvm-svn: 29664
 2006-08-14 19:01:24 +00:00
Chris Lattner
8ca6e82bce Eliminate use of getNode that takes a vector. 
llvm-svn: 29614
 2006-08-11 17:38:39 +00:00
Chris Lattner
be2765058e elimiante use of getNode that takes vector of operands. 
llvm-svn: 29612
 2006-08-11 17:22:35 +00:00
Evan Cheng
6053206580 Match tablegen changes. 
llvm-svn: 29604
 2006-08-11 09:08:15 +00:00
Rafael Espindola
f0b265b48b fix the spill code 
llvm-svn: 29583
 2006-08-09 16:41:12 +00:00
Rafael Espindola
7bfbb91f75 initial support for variable number of arguments 
llvm-svn: 29567
 2006-08-08 13:02:29 +00:00
Evan Cheng
d18be1d9c1 Match tablegen isel changes. 
llvm-svn: 29549
 2006-08-07 22:28:20 +00:00
Rafael Espindola
bd29d36be4 use a 'register pressure reducing' scheduler 
make sure only one move is used in a hello world

llvm-svn: 29520
 2006-08-04 12:48:42 +00:00
Rafael Espindola
97918b1d11 Bug fix: always generate a RET_FLAG in LowerRET 
fixes ret_null.ll and call.ll

llvm-svn: 29519
 2006-08-03 22:50:11 +00:00
Rafael Espindola
fa94338687 add and use ARMISD::RET_FLAG 
llvm-svn: 29499
 2006-08-03 17:02:20 +00:00
Rafael Espindola
f11277971f implement LowerConstantPool and LowerGlobalAddress 
llvm-svn: 29433
 2006-08-01 12:58:43 +00:00
Evan Cheng
3b5f1c6248 Remove InFlightSet hack. No longer needed. 
llvm-svn: 29373
 2006-07-28 00:47:19 +00:00
Rafael Espindola
2919d4ce24 implement function calling of functions with up to 4 arguments 
llvm-svn: 29274
 2006-07-25 20:17:20 +00:00
Rafael Espindola
40073f5767 skeleton of a lowerCall implementation for ARM 
llvm-svn: 29159
 2006-07-16 01:02:57 +00:00
Rafael Espindola
fdfaee67f5 add the memri memory operand 
this makes it possible for ldr instructions with non-zero immediate

llvm-svn: 29103
 2006-07-11 11:36:48 +00:00
Rafael Espindola
071c83dff0 create the raddr addressing mode that matches any register and the frame index 
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot

llvm-svn: 29079
 2006-07-10 01:41:35 +00:00
Rafael Espindola
f11f34a3d6 handle the "mov reg1, reg2" case in isMoveInstr 
llvm-svn: 28945
 2006-06-27 21:52:45 +00:00
Rafael Espindola
bcba226a99 lower more then 4 formal arguments. The offset is currently hard coded. 
implement SelectFrameIndex

llvm-svn: 28751
 2006-06-12 12:28:08 +00:00
Rafael Espindola
42375303a6 add R0 to liveout 
expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch

llvm-svn: 28691
 2006-06-05 22:26:14 +00:00
Rafael Espindola
1bf57da16e Expand ret into "CopyToReg;BRIND" 
llvm-svn: 28559
 2006-05-30 17:33:19 +00:00
Evan Cheng
de0f25081a Change RET node to include signness information of the return values. i.e. 
RET chain, value1, sign1, value2, sign2, ...

llvm-svn: 28510
 2006-05-26 23:10:12 +00:00
Rafael Espindola
90eec6b0f7 port the ARM backend to use ISD::CALL instead of LowerCallTo 
llvm-svn: 28469
 2006-05-25 11:00:18 +00:00
Evan Cheng
09942d3f8b Assert if InflightSet is not cleared after instruction selecting a BB. 
llvm-svn: 28459
 2006-05-25 00:24:28 +00:00
Evan Cheng
b040dd86af Clear HandleMap and ReplaceMap after instruction selection. Or it may cause 
non-deterministic behavior.

llvm-svn: 28454
 2006-05-24 20:46:25 +00:00
Chris Lattner
f604017e47 Patches to make the LLVM sources more -pedantic clean. Patch provided 
by Anton Korobeynikov!  This is a step towards closing PR786.

llvm-svn: 28447
 2006-05-24 17:04:05 +00:00
Rafael Espindola
bb1e2e2c52 implement minimal versions of 
ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr

llvm-svn: 28431
 2006-05-23 02:48:20 +00:00
Rafael Espindola
a0e82ff9be implement movri 
add a stub LowerFORMAL_ARGUMENTS

llvm-svn: 28388
 2006-05-18 21:45:49 +00:00
Rafael Espindola
c928207091 add an abort after every assert(0) 
llvm-svn: 28310
 2006-05-15 22:34:39 +00:00
Rafael Espindola
dd49dfc0df added a skeleton of the ARM backend 
llvm-svn: 28301
 2006-05-14 22:18:28 +00:00