Hrvoje Varga
9f2ecb7f7a
[mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 instructions
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Differential Revision: http://reviews.llvm.org/D11292#inline-103143
llvm-svn: 250381
2015-10-15 08:39:07 +00:00
Hrvoje Varga
14f985bea0
[mips][microMIPS] Implement LLE and SCE instructions
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Differential Revision: http://reviews.llvm.org/D11630
llvm-svn: 250379
2015-10-15 08:11:50 +00:00
Hrvoje Varga
d0abe7e77c
[mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions
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Differential Revision: http://reviews.llvm.org/D11631
llvm-svn: 250377
2015-10-15 07:23:06 +00:00
Zoran Jovanovic
127b40176f
[mips][microMIPS] Implement JALRC16, JRCADDIUSP and JRC16 instructions
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Differential Revision: http://reviews.llvm.org/D11219
llvm-svn: 249317
2015-10-05 14:00:09 +00:00
Daniel Sanders
eab8334657
[mips][sched] Split IIBranch into specific instruction classes.
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Summary:
Almost no functional change since the InstrItinData's have been duplicated.
The one functional change is to remove IIBranch from the MSA branches. The
classes will be assigned to the MSA instructions as part of implementing
the P5600 scheduler.
II_IndirectBranchPseudo and II_ReturnPseudo can probably be removed. I've
preserved the itinerary information for the corresponding pseudo
instructions to avoid making a functional change to these pseudos in
this patch.
Reviewers: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D12189
llvm-svn: 248273
2015-09-22 13:36:28 +00:00
Daniel Sanders
d5bb1c9800
[mips][sched] Added class for WSBH
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Summary:
No functional change since no InstrItinData is provided.
Reviewers: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D12190
llvm-svn: 248257
2015-09-22 10:01:13 +00:00
Zoran Jovanovic
e19628ae40
[mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructions
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Differential Revision: http://reviews.llvm.org/D9658
llvm-svn: 247880
2015-09-17 10:14:09 +00:00
Zoran Jovanovic
b115382747
[mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and SWE instructions
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Differential Revision: http://reviews.llvm.org/D9189
llvm-svn: 247780
2015-09-16 09:14:35 +00:00
Zoran Jovanovic
cb8b3d36cb
[mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions
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Differential Revision: http://reviews.llvm.org/D11178
llvm-svn: 247146
2015-09-09 13:55:45 +00:00
Zoran Jovanovic
18ded41e82
[mips][microMIPS] Implement CACHEE and PREFE instructions
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Differential Revision: http://reviews.llvm.org/D11628
llvm-svn: 247125
2015-09-09 09:10:46 +00:00
Zoran Jovanovic
9ee500e089
[mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions
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Differential Revision: http://reviews.llvm.org/D11181
llvm-svn: 246963
2015-09-07 11:56:37 +00:00
Zoran Jovanovic
729cee7955
[mips][microMIPS] Implement BREAK, EHB and EI instructions
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http://reviews.llvm.org/D10090
llvm-svn: 240531
2015-06-24 10:32:16 +00:00
Jozef Kolek
3f22787f2e
[mips][microMIPS] Make usage of NOT16 by code generator
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Differential Revision: http://reviews.llvm.org/D7748
llvm-svn: 231963
2015-03-11 20:28:31 +00:00
Jozef Kolek
3042d386a1
[mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator
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Differential Revision: http://reviews.llvm.org/D7609
llvm-svn: 231249
2015-03-04 15:47:42 +00:00
Jozef Kolek
6455b0cb7f
Reversed revision 229706. The reason is regression, which is caused by the
...
usage of instruction ADDU16 by CodeGen. For this instruction an improper
register is allocated, i.e. the register that is not from register set defined
for the instruction.
llvm-svn: 230053
2015-02-20 20:26:52 +00:00
Jozef Kolek
6b4e19ed7b
[mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator
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Differential Revision: http://reviews.llvm.org/D7609
llvm-svn: 229706
2015-02-18 17:33:56 +00:00
Jozef Kolek
107ac262c2
[mips][microMIPS] Implement JALX instruction
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Differential Revision: http://reviews.llvm.org/D5047
llvm-svn: 229702
2015-02-18 17:15:48 +00:00
Zoran Jovanovic
7f0e9478f6
[mips][microMIPS] Implement movep instruction
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Differential Revision: http://reviews.llvm.org/D7465
llvm-svn: 228703
2015-02-10 16:36:20 +00:00
Jozef Kolek
3c2b5264df
[mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 and SWM16
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Differential Revision: http://reviews.llvm.org/D7436
llvm-svn: 228683
2015-02-10 12:41:13 +00:00
Zoran Jovanovic
8107003a7b
[mips][microMIPS] Implement CodeGen support for SW16 and LW16 instructions
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Differential Revision: http://reviews.llvm.org/D6581
llvm-svn: 228149
2015-02-04 15:43:17 +00:00
Zoran Jovanovic
9b40c3c637
[mips][microMIPS] Implement SWM and LWM aliases
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Differential Revision: http://reviews.llvm.org/D5820
llvm-svn: 227373
2015-01-28 21:52:27 +00:00
Jozef Kolek
e6b6be169a
[mips][microMIPS] Implement LWGP instruction
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Differential Revision: http://reviews.llvm.org/D6650
llvm-svn: 227325
2015-01-28 17:27:26 +00:00
Jozef Kolek
07bbffd274
[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B
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Implement microMIPS 16-bit unconditional branch instruction B.
Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1
Differential Revision: http://reviews.llvm.org/D3514
llvm-svn: 226657
2015-01-21 12:39:30 +00:00
Jozef Kolek
544ed14227
[mips][microMIPS] Implement ADDIUPC instruction
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Differential Revision: http://reviews.llvm.org/D6582
llvm-svn: 226656
2015-01-21 12:10:11 +00:00
Jozef Kolek
dc9fe311f2
Reverted revision 226577.
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llvm-svn: 226595
2015-01-20 19:29:28 +00:00
Jozef Kolek
ca8263125b
[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B
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Implement microMIPS 16-bit unconditional branch instruction B.
Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1
Differential Revision: http://reviews.llvm.org/D3514
llvm-svn: 226577
2015-01-20 16:45:27 +00:00
Jozef Kolek
c8014187bb
[mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions
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Differential Revision: http://reviews.llvm.org/D5271
llvm-svn: 225627
2015-01-12 12:03:34 +00:00
Jozef Kolek
a7fba787ce
[mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions
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Differential Revision: http://reviews.llvm.org/D5204
llvm-svn: 224785
2014-12-23 19:55:34 +00:00
Jozef Kolek
814723a8ed
[mips][microMIPS] Implement LWSP and SWSP instructions
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Differential Revision: http://reviews.llvm.org/D6416
llvm-svn: 224771
2014-12-23 16:16:33 +00:00
Zoran Jovanovic
d72dae73a8
[mips][microMIPS] Implement SWP and LWP instructions
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Differential Revision: http://reviews.llvm.org/D5667
llvm-svn: 224338
2014-12-16 14:59:10 +00:00
Jozef Kolek
3a4db003e2
[mips][microMIPS] Implement CodeGen support for LI16 instruction.
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Differential Revision: http://reviews.llvm.org/D5840
llvm-svn: 224017
2014-12-11 13:56:23 +00:00
Vladimir Medic
7915fd41c4
The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.
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llvm-svn: 223006
2014-12-01 11:12:04 +00:00
Jozef Kolek
e3a600e129
[mips][microMIPS] Implement NOP aliases
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This patch implements microMIPS 16-bit (MOVE16 $0, $0) and
32-bit (SLL $0, $0, 0) NOP aliases.
http://reviews.llvm.org/D6440
llvm-svn: 222953
2014-11-29 13:29:24 +00:00
Zoran Jovanovic
15712f82b0
[mips][microMIPS] Implement SWM16 and LWM16 instructions
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Differential Revision: http://reviews.llvm.org/D5579
llvm-svn: 222901
2014-11-27 18:28:59 +00:00
Jozef Kolek
c85a4a5656
[mips][microMIPS] Implement BREAK16 and SDBBP16 instructions
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Patch by Radovan Obradovic.
Differential Revision: http://reviews.llvm.org/D5048
llvm-svn: 222900
2014-11-27 18:18:42 +00:00
Jozef Kolek
90243462d4
[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5
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Differential Revision: http://reviews.llvm.org/D6419
llvm-svn: 222887
2014-11-27 14:41:44 +00:00
Jozef Kolek
ecfa20e7f7
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16
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Differential Revision: http://reviews.llvm.org/D6405
llvm-svn: 222847
2014-11-26 18:56:38 +00:00
Jozef Kolek
a4e87d7a74
[mips][microMIPS] Fix JRADDIUSP instruction
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Fix JRADDIUSP instruction, remove delay slot flag because this instruction
doesn't have delay slot.
Differential Revision: http://reviews.llvm.org/D6365
llvm-svn: 222658
2014-11-24 16:14:10 +00:00
Jozef Kolek
dd0dbf282b
[mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions
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Differential Revision: http://reviews.llvm.org/D5122
llvm-svn: 222653
2014-11-24 14:39:13 +00:00
Zoran Jovanovic
ebf19d975c
[mips][micromips] Implement SWM32 and LWM32 instructions
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Differential Revision: http://reviews.llvm.org/D5519
llvm-svn: 222367
2014-11-19 16:44:02 +00:00
Jozef Kolek
d19675f448
[mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2.
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Differential Revision: http://reviews.llvm.org/D5800
llvm-svn: 222352
2014-11-19 13:23:58 +00:00
Jozef Kolek
9fbf00198c
[mips][microMIPS] Implement CodeGen support for ADDIUS5 instruction.
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Differential Revision: http://reviews.llvm.org/D5799
llvm-svn: 222351
2014-11-19 13:11:09 +00:00
Jozef Kolek
0de52b5b97
[mips][microMIPS] Implement LWXS instruction.
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Differential Revision: http://reviews.llvm.org/D5407
llvm-svn: 222348
2014-11-19 11:39:12 +00:00
Jozef Kolek
e466cd5b54
[mips][microMIPS] Implement SDBBP and RDHWR instructions.
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Differential Revision: http://reviews.llvm.org/D5240
llvm-svn: 222347
2014-11-19 11:25:50 +00:00
Zoran Jovanovic
632c4a4f61
[mips][micromips] Add predicate 'InMicroMips' at CodeGen patterns for microMIPS instructions
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Differential Revision: http://reviews.llvm.org/D6198
llvm-svn: 221780
2014-11-12 13:30:10 +00:00
Zoran Jovanovic
f79dde9378
ps][microMIPS] Implement CodeGen support for ANDI16 instruction
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llvm-svn: 221371
2014-11-05 17:43:00 +00:00
Zoran Jovanovic
a0eca4a912
ps][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions
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llvm-svn: 221369
2014-11-05 17:38:31 +00:00
Zoran Jovanovic
3aa8010f59
[mips][microMIPS] Implement ANDI16 instruction
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llvm-svn: 221367
2014-11-05 17:31:00 +00:00
Zoran Jovanovic
9298c57c2a
Reverted revisions 221351, 221352 and 221353.
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llvm-svn: 221354
2014-11-05 16:19:59 +00:00
Zoran Jovanovic
59ff702bee
[mips][microMIPS] Implement CodeGen support for ANDI16 instruction
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Differential Revision: http://reviews.llvm.org/D5797
llvm-svn: 221353
2014-11-05 15:54:05 +00:00