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a8f0f7babb
Generate code for Mips32r1 unless a Mips32r2 feature is tested. llvm-svn: 139433
16 lines
299 B
LLVM
16 lines
299 B
LLVM
; RUN: llc -march=mips < %s | FileCheck %s
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; CHECK: mul $2, $5, $4
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define i32 @mul1(i32 %a, i32 %b) nounwind readnone {
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entry:
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%mul = mul i32 %b, %a
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ret i32 %mul
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}
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; CHECK: mul $2, $5, $4
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define i32 @mul2(i32 %a, i32 %b) nounwind readnone {
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entry:
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%mul = mul nsw i32 %b, %a
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ret i32 %mul
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}
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