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097bf66bf4
llvm-mirror/utils/TableGen
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Geoff Berry 097bf66bf4 [MachineOperand][Target] MachineOperand::isRenamable semantics changes 
Summary:
Add a target option AllowRegisterRenaming that is used to opt in to
post-register-allocation renaming of registers.  This is set to 0 by
default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
fields of all opcodes to be set to 1, causing
MachineOperand::isRenamable to always return false.

Set the AllowRegisterRenaming flag to 1 for all in-tree targets that
have lit tests that were effected by enabling COPY forwarding in
MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC,
RISCV, Sparc, SystemZ and X86).

Add some more comments describing the semantics of the
MachineOperand::isRenamable function and how it is set and maintained.

Change isRenamable to check the operand's opcode
hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of
relying on it being consistently reflected in the IsRenamable bit
setting.

Clear the IsRenamable bit when changing an operand's register value.

Remove target code that was clearing the IsRenamable bit when changing
registers/opcodes now that this is done conservatively by default.

Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in
one place covering all opcodes that have constant pipe read limit
restrictions.

Reviewers: qcolombet, MatzeB

Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D43042

llvm-svn: 325931
2018-02-23 18:25:08 +00:00
..
AsmMatcherEmitter.cpp Fix signed/unsigned comparison warning in AsmGenMatcher generated code. NFCI. 2018-02-17 12:29:47 +00:00
AsmWriterEmitter.cpp [AArch64][TableGen] Skip tied result operands for InstAlias 2017-11-20 14:36:40 +00:00
AsmWriterInst.cpp
AsmWriterInst.h
Attributes.cpp Remove redundant includes from utils/TableGen. 2017-12-13 21:31:13 +00:00
CallingConvEmitter.cpp [TableGen] Simplify CallingConvEmitter.cpp. NFC. 2017-10-16 14:52:26 +00:00
CMakeLists.txt TableGen: Allow setting SDNodeProperties on intrinsics 2017-12-20 19:36:28 +00:00
CodeEmitterGen.cpp [tablegen] Avoid creating a temporary vector in getInstructionCase 2017-07-04 06:16:53 +00:00
CodeGenDAGPatterns.cpp [TableGen] Add support of Intrinsics with multiple returns 2018-01-03 11:35:09 +00:00
CodeGenDAGPatterns.h [TableGen] Print more helpful information in case of type contradiction 2017-12-21 17:12:43 +00:00
CodeGenHwModes.cpp TableGen support for parameterized register class information 2017-09-14 16:56:21 +00:00
CodeGenHwModes.h TableGen support for parameterized register class information 2017-09-14 16:56:21 +00:00
CodeGenInstruction.cpp [globalisel][tablegen] Generalize pointer-type inference by introducing ptypeN. NFC 2017-11-18 00:16:44 +00:00
CodeGenInstruction.h [globalisel][tablegen] Generalize pointer-type inference by introducing ptypeN. NFC 2017-11-18 00:16:44 +00:00
CodeGenIntrinsics.h TableGen: Allow setting SDNodeProperties on intrinsics 2017-12-20 19:36:28 +00:00
CodeGenMapTable.cpp [mips] Improve diagnostics for instruction mapping 2018-01-08 16:25:40 +00:00
CodeGenRegisters.cpp [TableGen] Replace InfoByHwMode::getAsString with writeToStream 2017-09-22 18:29:37 +00:00
CodeGenRegisters.h TableGen support for parameterized register class information 2017-09-14 16:56:21 +00:00
CodeGenSchedule.cpp [CodeGenSchedule][NFC] Always emit ProcResourceUnits. 2018-02-05 12:23:51 +00:00
CodeGenSchedule.h [TableGen][NFC]Remove dead variable. 2018-01-26 13:21:43 +00:00
CodeGenTarget.cpp [MachineOperand][Target] MachineOperand::isRenamable semantics changes 2018-02-23 18:25:08 +00:00
CodeGenTarget.h [MachineOperand][Target] MachineOperand::isRenamable semantics changes 2018-02-23 18:25:08 +00:00
CTagsEmitter.cpp Revert r318822 "[llvm-tblgen] - Stop using std::string in RecordKeeper." 2017-11-23 06:52:44 +00:00
DAGISelEmitter.cpp Allow separation of declarations and definitions in <Target>ISelDAGToDAG.inc 2017-11-10 18:36:04 +00:00
DAGISelMatcher.cpp Remove redundant includes from utils/TableGen. 2017-12-13 21:31:13 +00:00
DAGISelMatcher.h Remove inline keyword from inline classof methods 2017-06-29 19:35:17 +00:00
DAGISelMatcherEmitter.cpp [SelectionDAG] Add a isel matcher op to check the type of node results other than result 0. 2017-11-22 07:11:01 +00:00
DAGISelMatcherGen.cpp TableGen support for parameterized register class information 2017-09-14 16:56:21 +00:00
DAGISelMatcherOpt.cpp [TableGen] Use less stack in DAGISelMatcherOpt 2017-02-06 19:41:44 +00:00
DFAPacketizerEmitter.cpp Avoid int to string conversion in Twine or raw_ostream contexts. 2017-12-28 16:58:54 +00:00
DisassemblerEmitter.cpp
FastISelEmitter.cpp Strip trailing whitespace 2017-10-06 15:33:55 +00:00
FixedLenDecoderEmitter.cpp [tablegen] Avoid creating temporary strings 2017-07-05 20:14:54 +00:00
GlobalISelEmitter.cpp [GISel]: Make GlobalISelEmitter rule prioritization compatible with selectionDAG 2018-02-16 22:37:15 +00:00
InfoByHwMode.cpp Remove redundant includes from utils/TableGen. 2017-12-13 21:31:13 +00:00
InfoByHwMode.h [TableGen] Replace InfoByHwMode::getAsString with writeToStream 2017-09-22 18:29:37 +00:00
InstrDocsEmitter.cpp [Docs] Add tablegen backend for target opcode documentation 2017-11-14 15:35:15 +00:00
InstrInfoEmitter.cpp [MachineOperand][Target] MachineOperand::isRenamable semantics changes 2018-02-23 18:25:08 +00:00
IntrinsicEmitter.cpp Avoid int to string conversion in Twine or raw_ostream contexts. 2017-12-28 16:58:54 +00:00
LLVMBuild.txt
OptParserEmitter.cpp [Bash-autocompletion] Add support for -std= 2017-08-29 02:01:56 +00:00
PseudoLoweringEmitter.cpp
RegisterBankEmitter.cpp [globalisel][regbank] Warn about MIR ambiguities when register bank/class names clash. 2017-11-01 22:13:05 +00:00
RegisterInfoEmitter.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
SDNodeProperties.cpp TableGen: Allow setting SDNodeProperties on intrinsics 2017-12-20 19:36:28 +00:00
SDNodeProperties.h TableGen: Allow setting SDNodeProperties on intrinsics 2017-12-20 19:36:28 +00:00
SearchableTableEmitter.cpp Remove redundant includes from utils/TableGen. 2017-12-13 21:31:13 +00:00
SequenceToOffsetTable.h Remove usages of deprecated std::unary_function and std::binary_function. 2017-09-14 18:33:25 +00:00
SubtargetEmitter.cpp [TargetSchedule] Fix r324582. 2018-02-09 10:28:46 +00:00
SubtargetFeatureInfo.cpp Reverting r315590; it did not include changes for llvm-tblgen, which is causing link errors for several people. 2017-10-15 14:32:27 +00:00
SubtargetFeatureInfo.h [globalisel][tablegen] Compute available feature bits correctly. 2017-04-29 17:30:09 +00:00
TableGen.cpp Remove redundant includes from utils/TableGen. 2017-12-13 21:31:13 +00:00
TableGenBackends.h [Docs] Add tablegen backend for target opcode documentation 2017-11-14 15:35:15 +00:00
tdtags
Types.cpp [globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule. 2017-04-21 15:59:56 +00:00
Types.h
X86DisassemblerShared.h
X86DisassemblerTables.cpp [X86][3DNOW] Teach decoder about AMD 3DNow! instrs 2018-02-15 21:20:31 +00:00
X86DisassemblerTables.h [X86] Fix disassembler table generation to prevent instructions tagged with 'PS' being inherited into PD/XS/XD attribute entries. 2017-10-23 16:49:26 +00:00
X86EVEX2VEXTablesEmitter.cpp [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass. 2018-02-13 04:19:26 +00:00
X86FoldTablesEmitter.cpp [X86] Don't put any EVEX_B instructions in the tablegen generated load folding tables. 2018-01-07 06:24:28 +00:00
X86ModRMFilters.cpp
X86ModRMFilters.h fix trivial typos in comments; NFC 2017-07-04 13:09:29 +00:00
X86RecognizableInstr.cpp [X86][3DNOW] Teach decoder about AMD 3DNow! instrs 2018-02-15 21:20:31 +00:00
X86RecognizableInstr.h [X86][3DNOW] Teach decoder about AMD 3DNow! instrs 2018-02-15 21:20:31 +00:00