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607f7c19c2
bswap.v2i16 + sitofp in LLVM IR generate a sequence of: - REV32 + USHR for bswap.v2i16 - SHL + SSHR + SCVTF for sext to v2i32 and scvt The shift instructions are excessive as noted in PR24820, and they can be optimized to just SSHR. Differential Revision: https://reviews.llvm.org/D102333
28 lines
914 B
LLVM
28 lines
914 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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define <2 x i32> @test1(<2 x i16> %v2i16) {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev32 v0.8b, v0.8b
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; CHECK-NEXT: sshr v0.2s, v0.2s, #16
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; CHECK-NEXT: ret
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%v2i16_rev = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %v2i16)
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%v2i32 = sext <2 x i16> %v2i16_rev to <2 x i32>
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ret <2 x i32> %v2i32
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}
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define <2 x float> @test2(<2 x i16> %v2i16) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev32 v0.8b, v0.8b
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; CHECK-NEXT: sshr v0.2s, v0.2s, #16
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; CHECK-NEXT: scvtf v0.2s, v0.2s
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; CHECK-NEXT: ret
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%v2i16_rev = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %v2i16)
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%v2f32 = sitofp <2 x i16> %v2i16_rev to <2 x float>
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ret <2 x float> %v2f32
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}
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declare <2 x i16> @llvm.bswap.v2i16(<2 x i16>) nounwind readnone
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