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211286ee5b
D75689 turns the faddp pattern into a shuffle with vector add. Match this new pattern in target-specific DAG combine, rather than ISel, because legalization (for v2f32) turns it into a bit of a mess. - extended to cover f16, f32, f64 and i64
142 lines
5.0 KiB
LLVM
142 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=aarch64 -mattr=+fullfp16 < %s | FileCheck %s
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; RUN: llc --mtriple=aarch64 < %s | FileCheck %s --check-prefix=CHECKNOFP16
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define half @faddp_2xhalf(<2 x half> %a) {
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; CHECK-LABEL: faddp_2xhalf:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: faddp h0, v0.2h
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; CHECK-NEXT: ret
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;
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; CHECKNOFP16-LABEL: faddp_2xhalf:
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; CHECKNOFP16: // %bb.0: // %entry
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; CHECKNOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECKNOFP16-NEXT: dup v1.4h, v0.h[1]
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; CHECKNOFP16-NEXT: fcvtl v1.4s, v1.4h
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; CHECKNOFP16-NEXT: fcvtl v0.4s, v0.4h
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; CHECKNOFP16-NEXT: fadd v0.4s, v0.4s, v1.4s
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; CHECKNOFP16-NEXT: fcvtn v0.4h, v0.4s
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; CHECKNOFP16-NEXT: // kill: def $h0 killed $h0 killed $q0
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; CHECKNOFP16-NEXT: ret
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entry:
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%shift = shufflevector <2 x half> %a, <2 x half> undef, <2 x i32> <i32 1, i32 undef>
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%0 = fadd <2 x half> %a, %shift
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%1 = extractelement <2 x half> %0, i32 0
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ret half %1
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}
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define half @faddp_2xhalf_commute(<2 x half> %a) {
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; CHECK-LABEL: faddp_2xhalf_commute:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: faddp h0, v0.2h
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; CHECK-NEXT: ret
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;
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; CHECKNOFP16-LABEL: faddp_2xhalf_commute:
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; CHECKNOFP16: // %bb.0: // %entry
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; CHECKNOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECKNOFP16-NEXT: dup v1.4h, v0.h[1]
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; CHECKNOFP16-NEXT: fcvtl v1.4s, v1.4h
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; CHECKNOFP16-NEXT: fcvtl v0.4s, v0.4h
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; CHECKNOFP16-NEXT: fadd v0.4s, v1.4s, v0.4s
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; CHECKNOFP16-NEXT: fcvtn v0.4h, v0.4s
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; CHECKNOFP16-NEXT: // kill: def $h0 killed $h0 killed $q0
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; CHECKNOFP16-NEXT: ret
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entry:
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%shift = shufflevector <2 x half> %a, <2 x half> undef, <2 x i32> <i32 1, i32 undef>
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%0 = fadd <2 x half> %shift, %a
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%1 = extractelement <2 x half> %0, i32 0
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ret half %1
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}
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define half @faddp_4xhalf(<4 x half> %a) {
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; CHECK-LABEL: faddp_4xhalf:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: faddp h0, v0.2h
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; CHECK-NEXT: ret
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;
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; CHECKNOFP16-LABEL: faddp_4xhalf:
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; CHECKNOFP16: // %bb.0: // %entry
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; CHECKNOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECKNOFP16-NEXT: dup v1.4h, v0.h[1]
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; CHECKNOFP16-NEXT: fcvtl v1.4s, v1.4h
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; CHECKNOFP16-NEXT: fcvtl v0.4s, v0.4h
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; CHECKNOFP16-NEXT: fadd v0.4s, v0.4s, v1.4s
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; CHECKNOFP16-NEXT: fcvtn v0.4h, v0.4s
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; CHECKNOFP16-NEXT: // kill: def $h0 killed $h0 killed $q0
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; CHECKNOFP16-NEXT: ret
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entry:
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%shift = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%0 = fadd <4 x half> %a, %shift
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%1 = extractelement <4 x half> %0, i32 0
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ret half %1
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}
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define half @faddp_4xhalf_commute(<4 x half> %a) {
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; CHECK-LABEL: faddp_4xhalf_commute:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: faddp h0, v0.2h
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; CHECK-NEXT: ret
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;
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; CHECKNOFP16-LABEL: faddp_4xhalf_commute:
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; CHECKNOFP16: // %bb.0: // %entry
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; CHECKNOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECKNOFP16-NEXT: dup v1.4h, v0.h[1]
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; CHECKNOFP16-NEXT: fcvtl v1.4s, v1.4h
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; CHECKNOFP16-NEXT: fcvtl v0.4s, v0.4h
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; CHECKNOFP16-NEXT: fadd v0.4s, v1.4s, v0.4s
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; CHECKNOFP16-NEXT: fcvtn v0.4h, v0.4s
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; CHECKNOFP16-NEXT: // kill: def $h0 killed $h0 killed $q0
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; CHECKNOFP16-NEXT: ret
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entry:
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%shift = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%0 = fadd <4 x half> %shift, %a
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%1 = extractelement <4 x half> %0, i32 0
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ret half %1
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}
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define half @faddp_8xhalf(<8 x half> %a) {
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; CHECK-LABEL: faddp_8xhalf:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: faddp h0, v0.2h
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; CHECK-NEXT: ret
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;
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; CHECKNOFP16-LABEL: faddp_8xhalf:
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; CHECKNOFP16: // %bb.0: // %entry
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; CHECKNOFP16-NEXT: dup v1.8h, v0.h[1]
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; CHECKNOFP16-NEXT: fcvt s0, h0
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; CHECKNOFP16-NEXT: fcvt s1, h1
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; CHECKNOFP16-NEXT: fadd s0, s0, s1
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; CHECKNOFP16-NEXT: fcvt h0, s0
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; CHECKNOFP16-NEXT: ret
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entry:
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%shift = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%0 = fadd <8 x half> %a, %shift
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%1 = extractelement <8 x half> %0, i32 0
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ret half %1
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}
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define half @faddp_8xhalf_commute(<8 x half> %a) {
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; CHECK-LABEL: faddp_8xhalf_commute:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: faddp h0, v0.2h
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; CHECK-NEXT: ret
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;
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; CHECKNOFP16-LABEL: faddp_8xhalf_commute:
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; CHECKNOFP16: // %bb.0: // %entry
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; CHECKNOFP16-NEXT: dup v1.8h, v0.h[1]
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; CHECKNOFP16-NEXT: fcvt s0, h0
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; CHECKNOFP16-NEXT: fcvt s1, h1
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; CHECKNOFP16-NEXT: fadd s0, s1, s0
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; CHECKNOFP16-NEXT: fcvt h0, s0
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; CHECKNOFP16-NEXT: ret
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entry:
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%shift = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%0 = fadd <8 x half> %shift, %a
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%1 = extractelement <8 x half> %0, i32 0
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ret half %1
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}
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