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c9256d3620
X86 and AArch64 expand it as libcall inside the target. And PowerPC also want to expand them as libcall for P8. So, propose an implement in the legalizer to common the logic and remove the code for X86/AArch64 to avoid the duplicate code. Reviewed By: Craig Topper Differential Revision: https://reviews.llvm.org/D91331
235 lines
7.7 KiB
LLVM
235 lines
7.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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; Same as vecreduce-fadd-legalization.ll, but without fmf.
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declare half @llvm.vector.reduce.fadd.f16.v1f16(half, <1 x half>)
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declare float @llvm.vector.reduce.fadd.f32.v1f32(float, <1 x float>)
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declare double @llvm.vector.reduce.fadd.f64.v1f64(double, <1 x double>)
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declare fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128, <1 x fp128>)
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declare float @llvm.vector.reduce.fadd.f32.v3f32(float, <3 x float>)
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declare float @llvm.vector.reduce.fadd.f32.v5f32(float, <5 x float>)
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declare fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128, <2 x fp128>)
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declare float @llvm.vector.reduce.fadd.f32.v16f32(float, <16 x float>)
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define half @test_v1f16(<1 x half> %a, half %s) nounwind {
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; CHECK-LABEL: test_v1f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fcvt s1, h1
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; CHECK-NEXT: fadd s0, s1, s0
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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%b = call half @llvm.vector.reduce.fadd.f16.v1f16(half %s, <1 x half> %a)
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ret half %b
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}
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define half @test_v1f16_neutral(<1 x half> %a) nounwind {
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; CHECK-LABEL: test_v1f16_neutral:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call half @llvm.vector.reduce.fadd.f16.v1f16(half -0.0, <1 x half> %a)
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ret half %b
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}
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define float @test_v1f32(<1 x float> %a, float %s) nounwind {
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; CHECK-LABEL: test_v1f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: fadd s0, s1, s0
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; CHECK-NEXT: ret
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%b = call float @llvm.vector.reduce.fadd.f32.v1f32(float %s, <1 x float> %a)
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ret float %b
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}
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define float @test_v1f32_neutral(<1 x float> %a) nounwind {
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; CHECK-LABEL: test_v1f32_neutral:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
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; CHECK-NEXT: ret
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%b = call float @llvm.vector.reduce.fadd.f32.v1f32(float -0.0, <1 x float> %a)
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ret float %b
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}
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define double @test_v1f64(<1 x double> %a, double %s) nounwind {
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; CHECK-LABEL: test_v1f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fadd d0, d1, d0
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; CHECK-NEXT: ret
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%b = call double @llvm.vector.reduce.fadd.f64.v1f64(double %s, <1 x double> %a)
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ret double %b
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}
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define double @test_v1f64_neutral(<1 x double> %a) nounwind {
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; CHECK-LABEL: test_v1f64_neutral:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call double @llvm.vector.reduce.fadd.f64.v1f64(double -0.0, <1 x double> %a)
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ret double %b
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}
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define fp128 @test_v1f128(<1 x fp128> %a, fp128 %s) nounwind {
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; CHECK-LABEL: test_v1f128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov v2.16b, v0.16b
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; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: mov v1.16b, v2.16b
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; CHECK-NEXT: b __addtf3
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%b = call fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128 %s, <1 x fp128> %a)
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ret fp128 %b
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}
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define fp128 @test_v1f128_neutral(<1 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v1f128_neutral:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128 0xL00000000000000008000000000000000, <1 x fp128> %a)
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ret fp128 %b
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}
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define float @test_v3f32(<3 x float> %a, float %s) nounwind {
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; CHECK-LABEL: test_v3f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fadd s1, s1, s0
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; CHECK-NEXT: mov s2, v0.s[1]
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; CHECK-NEXT: fadd s1, s1, s2
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; CHECK-NEXT: mov s0, v0.s[2]
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; CHECK-NEXT: fadd s0, s1, s0
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; CHECK-NEXT: ret
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%b = call float @llvm.vector.reduce.fadd.f32.v3f32(float %s, <3 x float> %a)
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ret float %b
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}
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define float @test_v3f32_neutral(<3 x float> %a) nounwind {
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; CHECK-LABEL: test_v3f32_neutral:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov s1, v0.s[2]
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; CHECK-NEXT: faddp s0, v0.2s
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: ret
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%b = call float @llvm.vector.reduce.fadd.f32.v3f32(float -0.0, <3 x float> %a)
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ret float %b
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}
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define float @test_v5f32(<5 x float> %a, float %s) nounwind {
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; CHECK-LABEL: test_v5f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fadd s0, s5, s0
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: fadd s0, s0, s2
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; CHECK-NEXT: fadd s0, s0, s3
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; CHECK-NEXT: fadd s0, s0, s4
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; CHECK-NEXT: ret
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%b = call float @llvm.vector.reduce.fadd.f32.v5f32(float %s, <5 x float> %a)
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ret float %b
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}
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define float @test_v5f32_neutral(<5 x float> %a) nounwind {
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; CHECK-LABEL: test_v5f32_neutral:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: fadd s0, s0, s2
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; CHECK-NEXT: fadd s0, s0, s3
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; CHECK-NEXT: fadd s0, s0, s4
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; CHECK-NEXT: ret
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%b = call float @llvm.vector.reduce.fadd.f32.v5f32(float -0.0, <5 x float> %a)
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ret float %b
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}
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define fp128 @test_v2f128(<2 x fp128> %a, fp128 %s) nounwind {
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; CHECK-LABEL: test_v2f128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #32 // =32
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; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
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; CHECK-NEXT: mov v1.16b, v0.16b
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
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; CHECK-NEXT: bl __addtf3
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; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
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; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
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; CHECK-NEXT: add sp, sp, #32 // =32
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; CHECK-NEXT: b __addtf3
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%b = call fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 %s, <2 x fp128> %a)
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ret fp128 %b
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}
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define fp128 @test_v2f128_neutral(<2 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v2f128_neutral:
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; CHECK: // %bb.0:
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; CHECK-NEXT: b __addtf3
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%b = call fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 0xL00000000000000008000000000000000, <2 x fp128> %a)
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ret fp128 %b
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}
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define float @test_v16f32(<16 x float> %a, float %s) nounwind {
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; CHECK-LABEL: test_v16f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov s22, v0.s[3]
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; CHECK-NEXT: mov s23, v0.s[2]
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; CHECK-NEXT: mov s24, v0.s[1]
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; CHECK-NEXT: fadd s0, s4, s0
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; CHECK-NEXT: fadd s0, s0, s24
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; CHECK-NEXT: fadd s0, s0, s23
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; CHECK-NEXT: fadd s0, s0, s22
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; CHECK-NEXT: mov s21, v1.s[1]
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: mov s20, v1.s[2]
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; CHECK-NEXT: fadd s0, s0, s21
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; CHECK-NEXT: mov s19, v1.s[3]
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; CHECK-NEXT: fadd s0, s0, s20
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; CHECK-NEXT: fadd s0, s0, s19
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; CHECK-NEXT: mov s18, v2.s[1]
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; CHECK-NEXT: fadd s0, s0, s2
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; CHECK-NEXT: mov s17, v2.s[2]
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; CHECK-NEXT: fadd s0, s0, s18
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; CHECK-NEXT: mov s16, v2.s[3]
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; CHECK-NEXT: fadd s0, s0, s17
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; CHECK-NEXT: fadd s0, s0, s16
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; CHECK-NEXT: mov s7, v3.s[1]
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; CHECK-NEXT: fadd s0, s0, s3
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; CHECK-NEXT: mov s6, v3.s[2]
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; CHECK-NEXT: fadd s0, s0, s7
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; CHECK-NEXT: mov s5, v3.s[3]
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; CHECK-NEXT: fadd s0, s0, s6
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; CHECK-NEXT: fadd s0, s0, s5
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; CHECK-NEXT: ret
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%b = call float @llvm.vector.reduce.fadd.f32.v16f32(float %s, <16 x float> %a)
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ret float %b
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}
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define float @test_v16f32_neutral(<16 x float> %a) nounwind {
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; CHECK-LABEL: test_v16f32_neutral:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov s21, v0.s[3]
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; CHECK-NEXT: mov s22, v0.s[2]
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; CHECK-NEXT: faddp s0, v0.2s
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; CHECK-NEXT: fadd s0, s0, s22
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; CHECK-NEXT: fadd s0, s0, s21
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; CHECK-NEXT: mov s20, v1.s[1]
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: mov s19, v1.s[2]
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; CHECK-NEXT: fadd s0, s0, s20
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; CHECK-NEXT: mov s18, v1.s[3]
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; CHECK-NEXT: fadd s0, s0, s19
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; CHECK-NEXT: fadd s0, s0, s18
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; CHECK-NEXT: mov s17, v2.s[1]
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; CHECK-NEXT: fadd s0, s0, s2
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; CHECK-NEXT: mov s16, v2.s[2]
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; CHECK-NEXT: fadd s0, s0, s17
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; CHECK-NEXT: mov s7, v2.s[3]
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; CHECK-NEXT: fadd s0, s0, s16
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; CHECK-NEXT: fadd s0, s0, s7
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; CHECK-NEXT: mov s6, v3.s[1]
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; CHECK-NEXT: fadd s0, s0, s3
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; CHECK-NEXT: mov s5, v3.s[2]
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; CHECK-NEXT: fadd s0, s0, s6
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; CHECK-NEXT: mov s4, v3.s[3]
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; CHECK-NEXT: fadd s0, s0, s5
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; CHECK-NEXT: fadd s0, s0, s4
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; CHECK-NEXT: ret
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%b = call float @llvm.vector.reduce.fadd.f32.v16f32(float -0.0, <16 x float> %a)
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ret float %b
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}
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