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ae1dd01644
This patch exploits mtvsrdd instruction (available in ISA3.0+) to save two callee-saved GPR registers into a single VSR, making it more efficient. Reviewed By: jsji, nemanjai Differential Revision: https://reviews.llvm.org/D62565
69 lines
1.7 KiB
YAML
69 lines
1.7 KiB
YAML
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -run-pass=prologepilog -ppc-enable-pe-vector-spills %s -o - | FileCheck %s
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---
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name: test1BB
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alignment: 16
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tracksRegLiveness: true
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liveins:
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body: |
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bb.0.entry:
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$r14 = IMPLICIT_DEF
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$r15 = IMPLICIT_DEF
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$r16 = IMPLICIT_DEF
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$f0 = IMPLICIT_DEF
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$v20 = IMPLICIT_DEF
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BLR8 implicit undef $lr8, implicit undef $rm
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# Use mtvsrdd to save two GPRs in a single instruction
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# CHECK-LABEL: name: test1BB
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# CHECK: body: |
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# CHECK: liveins: $x14, $x15, $x16, $v20
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# CHECK: $v0 = MTVSRDD killed $x14, killed $x15
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# CHECK-NEXT: $vf1 = MTVSRD killed $x16
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# CHECK: $x16 = MFVSRD killed $vf1
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# CHECK-NEXT: $x15 = MFVSRLD $v0
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# CHECK-NEXT: $x14 = MFVSRD killed $vf0
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...
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---
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name: test2BBs
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alignment: 16
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tracksRegLiveness: true
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liveins:
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body: |
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bb.0.entry:
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successors: %bb.1, %bb.2
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$cr0 = IMPLICIT_DEF
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BCC 4, killed renamable $cr0, %bb.2
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B %bb.1
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bb.1:
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$r14 = IMPLICIT_DEF
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$r15 = IMPLICIT_DEF
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$r16 = IMPLICIT_DEF
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$r3 = IMPLICIT_DEF
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B %bb.3
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bb.2:
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$r3 = IMPLICIT_DEF
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bb.3:
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BLR8 implicit undef $lr8, implicit undef $rm
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## The spilled-to registers have to be marked as live-in so that they will not be
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## clobbered before restored in the epilogue.
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# CHECK-LABEL: name: test2BB
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# CHECK: body: |
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# CHECK: $v0 = MTVSRDD killed $x14, killed $x15
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# CHECK-NEXT: $vf1 = MTVSRD killed $x16
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# CHECK: bb.2:
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# CHECK-NEXT: successors: %bb.3
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# CHECK-NEXT: liveins: $v0, $v1
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# CHECK: bb.3:
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# CHECK-NEXT: liveins: $v0, $v1
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# CHECK: $x16 = MFVSRD killed $vf1
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# CHECK-NEXT: $x15 = MFVSRLD $v0
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# CHECK-NEXT: $x14 = MFVSRD killed $vf0
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...
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