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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
49 lines
1.3 KiB
YAML
49 lines
1.3 KiB
YAML
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a57 -enable-unsafe-fp-math \
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# RUN: -run-pass machine-combiner -machine-combiner-inc-threshold=0 \
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# RUN: -machine-combiner-verify-pattern-order=true -verify-machineinstrs -o - %s | FileCheck %s
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---
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# Test incremental depth updates succeed when triggered after the removal of
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# the first instruction in a basic block.
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# CHECK-LABEL: name: inc_update_iterator_test
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name: inc_update_iterator_test
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registers:
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- { id: 0, class: fpr64 }
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- { id: 1, class: gpr32 }
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- { id: 2, class: gpr32 }
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- { id: 3, class: gpr32 }
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- { id: 4, class: gpr32 }
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- { id: 5, class: gpr32 }
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- { id: 6, class: gpr32 }
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- { id: 7, class: fpr64 }
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- { id: 8, class: fpr64 }
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- { id: 9, class: fpr64 }
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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%3 = COPY $w2
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%2 = COPY $w1
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%1 = COPY $w0
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%0 = COPY $d0
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%4 = SUBSWrr %1, %2, implicit-def $nzcv
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Bcc 13, %bb.2, implicit $nzcv
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B %bb.1
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bb.1:
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; CHECK: MADDWrrr %1, %2, %3
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%5 = MADDWrrr %1, %2, $wzr
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%6 = ADDWrr %3, killed %5
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%7 = SCVTFUWDri killed %6
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; CHECK: FMADDDrrr %7, %7, %0
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%8 = FMULDrr %7, %7
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%9 = FADDDrr %0, killed %8
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$d0 = COPY %9
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RET_ReallyLR implicit $d0
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bb.2:
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$d0 = COPY %0
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RET_ReallyLR implicit $d0
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...
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