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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
28 lines
825 B
YAML
28 lines
825 B
YAML
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# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt -verify-machineinstrs -o - %s | FileCheck %s
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--- |
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define i1 @no-clobber-zr(i64* %p, i64 %x) { ret i1 0 }
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...
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---
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# Check that write of xzr doesn't inhibit pairing of xzr stores since
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# it isn't actually clobbered. Written as a MIR test to avoid
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# schedulers reordering instructions such that SUBS doesn't appear
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# between stores.
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# CHECK-LABEL: name: no-clobber-zr
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# CHECK: STPXi $xzr, $xzr, $x0, 0
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name: no-clobber-zr
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body: |
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bb.0:
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liveins: $x0, $x1
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STRXui $xzr, $x0, 0 :: (store 8 into %ir.p)
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dead $xzr = SUBSXri killed $x1, 0, 0, implicit-def $nzcv
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$w8 = CSINCWr $wzr, $wzr, 1, implicit killed $nzcv
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STRXui $xzr, killed $x0, 1 :: (store 8 into %ir.p)
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$w0 = ORRWrs $wzr, killed $w8, 0
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RET $lr, implicit $w0
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...
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