Ana Pazos d1818e7c07 [RISCV] Fix decoding of invalid instruction with C extension enabled. ... Summary: The illegal instruction 0x00 0x00 is being wrongly decoded as c.addi4spn with 0 immediate. The invalid instruction 0x01 0x61 is being wrongly decoded as c.addi16sp with 0 immediate. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D51815 llvm-svn: 342159		2018-09-13 18:21:19 +00:00
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fuzzer-invalid.txt
invalid-fp-rounding-mode.txt
invalid-instruction.txt	[RISCV] Fix decoding of invalid instruction with C extension enabled.	2018-09-13 18:21:19 +00:00
lit.local.cfg