Pirama Arumuga Nainar 1fd184f18d Remove unsafe AssertZext after promoting result of FP_TO_FP16 ... Summary: Some target lowerings of FP_TO_FP16, for instance ARM's vcvtb.f16.f32 instruction, do not guarantee that the top 16 bits are zeroed out. Remove the unsafe AssertZext and add tests to exercise this. Reviewers: jmolloy, sbaranga, kristof.beyls, aadg Subscribers: llvm-commits, srhines, aemerson Differential Revision: http://reviews.llvm.org/D18426 llvm-svn: 264285		2016-03-24 14:06:03 +00:00
..
CMakeLists.txt	Rename TargetSelectionDAGInfo into SelectionDAGTargetInfo and move it to CodeGen/	2016-01-27 16:32:26 +00:00
DAGCombiner.cpp	SelectionDAG: Remove a tautological dyn_cast. NFC	2016-03-23 18:15:33 +00:00
FastISel.cpp	Add "first class" lowering for deopt operand bundles	2016-03-22 00:59:13 +00:00
FunctionLoweringInfo.cpp	[X86] Don't give catch objects a displacement of zero	2016-03-03 00:01:25 +00:00
InstrEmitter.cpp	[X86] Part 1 to fix x86-64 fp128 calling convention.	2015-12-03 22:02:40 +00:00
InstrEmitter.h
LegalizeDAG.cpp	CodeGen: check return types match when emitting tail call to builtin.	2016-03-22 19:14:38 +00:00
LegalizeFloatTypes.cpp	Do not try to use i8 and i16 versions of FP_TO_U/SINT soft float library calls	2015-12-15 12:55:50 +00:00
LegalizeIntegerTypes.cpp	Remove unsafe AssertZext after promoting result of FP_TO_FP16	2016-03-24 14:06:03 +00:00
LegalizeTypes.cpp	Revert "[mips] Promote the result of SETCC nodes to GPR width."	2016-03-01 20:25:43 +00:00
LegalizeTypes.h	[X86][SSE] Reapplied: Simplify vector LOAD + EXTEND on pre-SSE41 hardware	2016-03-22 16:22:08 +00:00
LegalizeTypesGeneric.cpp	[X86] Part 1 to fix x86-64 fp128 calling convention.	2015-12-03 22:02:40 +00:00
LegalizeVectorOps.cpp	[X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG	2016-03-10 20:40:26 +00:00
LegalizeVectorTypes.cpp	[X86][SSE] Reapplied: Simplify vector LOAD + EXTEND on pre-SSE41 hardware	2016-03-22 16:22:08 +00:00
LLVMBuild.txt
ResourcePriorityQueue.cpp
ScheduleDAGFast.cpp	Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef.	2015-12-05 07:13:35 +00:00
ScheduleDAGRRList.cpp	rangify; NFCI	2016-02-03 22:44:14 +00:00
ScheduleDAGSDNodes.cpp	Avoid overly large SmallPtrSet/SmallSet	2016-01-30 01:24:31 +00:00
ScheduleDAGSDNodes.h
ScheduleDAGVLIW.cpp
SDNodeDbgValue.h
SelectionDAG.cpp	[SelectionDAG] Ensure constant folded legalized vector element types are compatible with the BUILD_VECTOR type	2016-03-22 19:59:53 +00:00
SelectionDAGBuilder.cpp	Add a hasOperandBundlesOtherThan helper, and use it; NFC	2016-03-22 17:51:25 +00:00
SelectionDAGBuilder.h	Remove stale comment	2016-03-23 02:28:35 +00:00
SelectionDAGDumper.cpp	Avoid overly large SmallPtrSet/SmallSet	2016-01-30 01:24:31 +00:00
SelectionDAGISel.cpp	[CXX_FAST_TLS] fix issues with O0 on ARM, AArch64 and X86.	2016-03-18 23:38:49 +00:00
SelectionDAGPrinter.cpp
SelectionDAGTargetInfo.cpp	Rename TargetSelectionDAGInfo into SelectionDAGTargetInfo and move it to CodeGen/	2016-01-27 16:32:26 +00:00
StatepointLowering.cpp	[StatepointLowering] Minor nfc refactoring	2016-03-23 02:24:10 +00:00
StatepointLowering.h	[StatepointLowering] Don't do two DenseMap lookups; nfci	2016-03-23 02:24:15 +00:00
TargetLowering.cpp	[DAG] use !isUndef() ; NFCI	2016-03-14 18:09:43 +00:00