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llvm-mirror/test/CodeGen
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Simon Pilgrim 21c8bacf4a [X86][SSE] Swap X86ISD::BLENDV inputs with an inverted selection mask (PR42825) 
As discussed on PR42825, if we are inverting the selection mask we can just swap the inputs and avoid the inversion.

Differential Revision: https://reviews.llvm.org/D65522

llvm-svn: 368438
2019-08-09 12:44:20 +00:00
..
AArch64
[AArch64] Set pref. func. align to 8 bytes on Neoverse E1 & Cortex-A65
2019-08-09 11:05:15 +00:00
AMDGPU
[MBP] Disable aggressive loop rotate in plain mode
2019-08-08 20:25:23 +00:00
ARC
…
ARM
[ARM][ParallelDSP] Replace SExt uses
2019-08-09 07:48:50 +00:00
AVR
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BPF
[Transforms] Do not drop !preserve.access.index metadata
2019-08-03 23:41:26 +00:00
Generic
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Hexagon
[MBP] Disable aggressive loop rotate in plain mode
2019-08-08 20:25:23 +00:00
Inputs
[CodeGen] Add stack protector tests where the guard gets re-assigned
2019-07-17 20:46:16 +00:00
Lanai
[SDAG] commute setcc operands to match a subtract
2019-07-10 23:23:54 +00:00
Mips
[Mips][Codegen] Fix fast-isel mixing of FGR64 and AFGR64 registers
2019-08-09 12:02:32 +00:00
MIR
[PowerPC][Peephole] Check if extsw's second operand is a virtual register
2019-08-02 03:14:17 +00:00
MSP430
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NVPTX
[NVPTX] Fix PR41651
2019-07-30 19:52:01 +00:00
PowerPC
[MBP] Disable aggressive loop rotate in plain mode
2019-08-08 20:25:23 +00:00
RISCV
[MBP] Disable aggressive loop rotate in plain mode
2019-08-08 20:25:23 +00:00
SPARC
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SystemZ
[SystemZ] Regenerate <8 x i31> store test
2019-07-29 09:49:23 +00:00
Thumb
[MBP] Disable aggressive loop rotate in plain mode
2019-08-08 20:25:23 +00:00
Thumb2
[ARM] Add support for MVE pre and post inc loads and stores
2019-08-08 15:27:58 +00:00
WebAssembly
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::EXTRACT_VECTOR_ELT
2019-08-08 10:37:03 +00:00
WinCFGuard
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WinEH
IR: print value numbers for unnamed function arguments
2019-08-03 14:28:34 +00:00
X86
[X86][SSE] Swap X86ISD::BLENDV inputs with an inverted selection mask (PR42825)
2019-08-09 12:44:20 +00:00
XCore
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