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llvm-mirror/test/CodeGen
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Simon Pilgrim b4c2d312b7 [DAG] SimplifyMultipleUseDemandedBits - drop unnecessary *_EXTEND_VECTOR_INREG cases 
For little endian targets, if we only need the lowest element and none of the extended bits then we can just use the (bitcasted) source vector directly.

We already do this in SimplifyDemandedBits, this adds the SimplifyMultipleUseDemandedBits equivalent.
2020-06-22 12:35:32 +01:00
..
AArch64
[CGP] Convert phi types
2020-06-21 15:54:17 +01:00
AMDGPU
[amdgpu] Fix REL32 relocations with negative offsets.
2020-06-21 23:09:03 -04:00
ARC
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ARM
[ARM][BFloat] Implement lowering of bf16 load/store intrinsics
2020-06-19 14:02:35 +00:00
AVR
[AVR] Fix miscompilation of zext + add
2020-06-18 16:51:37 +02:00
BPF
[BPF] fix a bug for BTF pointee type pruning
2020-06-17 15:13:46 -07:00
Generic
[LLParser] Delete temp CallInst when error occurs
2020-06-16 11:41:25 +08:00
Hexagon
Simplify MachineVerifier's block-successor verification.
2020-06-06 22:30:51 -04:00
Inputs
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Lanai
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Mips
[DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2))
2020-06-12 13:53:08 -04:00
MIR
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MSP430
Revert "[MSP430] Update register names"
2020-06-22 13:37:22 +03:00
NVPTX
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PowerPC
[PowerPC][Power10] Implement Vector Clear Left/Rightmost Bytes Builtins in LLVM/Clang
2020-06-20 18:29:16 -05:00
RISCV
[RISCV64] Emit correct lib call for fp(float/double) to ui/si
2020-06-18 19:34:16 +05:30
SPARC
[SPARC] Lower fp16 ops to libcalls
2020-06-10 19:15:26 -07:00
SystemZ
[SystemZ] Bugfix in storeLoadCanUseBlockBinary().
2020-06-17 09:49:31 +02:00
Thumb
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Thumb2
Revert "[CGP] Enable CodeGenPrepares phi type convertion."
2020-06-22 13:06:18 +02:00
VE
[VE] Support relocation information in MC layer
2020-06-15 11:24:53 +02:00
WebAssembly
[Target] As part of using inclusive language within the llvm project,
2020-06-20 00:06:39 -07:00
WinCFGuard
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WinEH
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X86
[DAG] SimplifyMultipleUseDemandedBits - drop unnecessary *_EXTEND_VECTOR_INREG cases
2020-06-22 12:35:32 +01:00
XCore
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