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llvm-mirror/test/CodeGen/AMDGPU/regcoalesce-prune.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

32 lines
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YAML

# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa-opencl -run-pass=simple-register-coalescing | FileCheck %s
---
# Checks for a bug where subregister liveranges were not properly pruned for
# an IMPLCITI_DEF that gets removed completely.
#
# CHECK-LABEL: name: func
# IMPLICIT_DEF should be gone without llc hitting assertion failures.
# CHECK-NOT: IMPLICIT_DEF
name: func
tracksRegLiveness: true
body: |
bb.0:
undef %5.sub1 = V_MOV_B32_e32 0, implicit $exec
%6 = COPY %5
S_CBRANCH_VCCZ %bb.2, implicit undef $vcc
bb.1:
%1 : sreg_32_xm0 = S_MOV_B32 0
undef %0.sub0 : sreg_64 = COPY %1
%0.sub1 = COPY %1
%4 : vreg_64 = COPY killed %0
%5 : vreg_64 = IMPLICIT_DEF
%6 : vreg_64 = COPY killed %4
bb.2:
%2 : vgpr_32 = V_CVT_F32_I32_e32 killed %5.sub1, implicit $exec
bb.3:
%3 : vgpr_32 = V_CVT_F32_I32_e32 killed %6.sub1, implicit $exec
S_ENDPGM
...