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5cfc836f21
Summary: With scalar stores, M0 is clobbered and therefore marked as implicitly defined. However, it is also dead. This fixes an assertion when the Greedy Register Allocator decides to optimize a spill/restore pair away again (via tryHintsRecoloring). Reviewers: arsenm Subscribers: qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33319 llvm-svn: 306375
23 lines
711 B
LLVM
23 lines
711 B
LLVM
; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs -stop-before=prologepilog < %s
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; Spill to SMEM clobbers M0. Check that the implicit-def dead operand is present
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; in the pseudo instructions.
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; CHECK-LABEL: {{^}}spill_sgpr:
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; CHECK: SI_SPILL_S32_SAVE {{.*}}, implicit-def dead %m0
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; CHECK: SI_SPILL_S32_RESTORE {{.*}}, implicit-def dead %m0
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define amdgpu_kernel void @spill_sgpr(i32 addrspace(1)* %out, i32 %in) #0 {
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%sgpr = call i32 asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 %in, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(i32 %sgpr) #0
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br label %ret
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ret:
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ret void
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}
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attributes #0 = { nounwind }
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