Florian Hahn 33f5bfd4ee [ARM] Set Defs = [CPSR] for COPY_STRUCT_BYVAL, as it clobbers CPSR. ... Fixes PR35023. Reviewers: MatzeB, t.p.northover, sunfish, qcolombet, efriedma Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D55909 llvm-svn: 349935		2018-12-21 18:07:10 +00:00
..
CGP	[ARM][NFC] Adding another test for armcgp	2018-12-06 15:13:44 +00:00
GlobalISel	[ARM GlobalISel] Support G_CONSTANT for Thumb2	2018-12-19 09:55:10 +00:00
Windows	[SchedModel] Fix for read advance cycles with implicit pseudo operands.	2018-10-30 15:04:40 +00:00
2006-11-10-CycleInDAG.ll
2007-01-19-InfiniteLoop.ll
2007-03-07-CombinerCrash.ll
2007-03-13-InstrSched.ll
2007-03-21-JoinIntervalsCrash.ll
2007-03-27-RegScavengerAssert.ll
2007-03-30-RegScavengerAssert.ll
2007-04-02-RegScavengerAssert.ll
2007-04-03-PEIBug.ll
2007-04-03-UndefinedSymbol.ll
2007-04-30-CombinerCrash.ll
2007-05-03-BadPostIndexedLd.ll
2007-05-07-tailmerge-1.ll
2007-05-09-tailmerge-2.ll
2007-05-14-InlineAsmCstCrash.ll
2007-05-14-RegScavengerAssert.ll
2007-05-22-tailmerge-3.ll
2007-05-23-BadPreIndexedStore.ll
2007-08-15-ReuseBug.ll
2008-02-04-LocalRegAllocBug.ll
2008-02-29-RegAllocLocal.ll
2008-03-05-SxtInRegBug.ll
2008-03-07-RegScavengerAssert.ll
2008-04-04-ScavengerAssert.ll
2008-04-10-ScavengerAssert.ll
2008-04-11-PHIofImpDef.ll
2008-05-19-LiveIntervalsBug.ll
2008-05-19-ScavengerAssert.ll
2008-07-17-Fdiv.ll
2008-07-24-CodeGenPrepCrash.ll
2008-08-07-AsmPrintBug.ll
2008-09-17-CoalescerBug.ll
2008-11-18-ScavengerAssert.ll
2009-02-16-SpillerBug.ll
2009-02-22-SoftenFloatVaArg.ll
2009-02-27-SpillerBug.ll
2009-03-07-SpillerBug.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
2009-03-09-AddrModeBug.ll
2009-04-06-AsmModifier.ll
2009-04-08-AggregateAddr.ll
2009-04-08-FloatUndef.ll
2009-04-08-FREM.ll
2009-04-09-RegScavengerAsm.ll
2009-05-05-DAGCombineBug.ll
2009-05-07-RegAllocLocal.ll
2009-05-11-CodePlacementCrash.ll
2009-05-18-InlineAsmMem.ll
2009-06-02-ISelCrash.ll
2009-06-04-MissingLiveIn.ll
2009-06-15-RegScavengerAssert.ll
2009-06-19-RegScavengerAssert.ll
2009-06-22-CoalescerBug.ll
2009-06-30-RegScavengerAssert2.ll
2009-06-30-RegScavengerAssert3.ll
2009-06-30-RegScavengerAssert4.ll
2009-06-30-RegScavengerAssert5.ll
2009-06-30-RegScavengerAssert.ll
2009-07-01-CommuteBug.ll
2009-07-09-asm-p-constraint.ll
2009-07-18-RewriterBug.ll
2009-07-22-ScavengerAssert.ll
2009-07-22-SchedulerAssert.ll
2009-07-29-VFP3Registers.ll
2009-08-02-RegScavengerAssert-Neon.ll
2009-08-04-RegScavengerAssert-2.ll
2009-08-04-RegScavengerAssert.ll
2009-08-15-RegScavenger-EarlyClobber.ll
2009-08-15-RegScavengerAssert.ll
2009-08-21-PostRAKill2.ll
2009-08-21-PostRAKill3.ll
2009-08-21-PostRAKill.ll
2009-08-26-ScalarToVector.ll
2009-08-27-ScalarToVector.ll
2009-08-29-ExtractEltf32.ll
2009-08-29-TooLongSplat.ll
2009-08-31-LSDA-Name.ll
2009-08-31-TwoRegShuffle.ll
2009-09-09-AllOnes.ll
2009-09-09-fpcmp-ole.ll
2009-09-10-postdec.ll
2009-09-13-InvalidSubreg.ll
2009-09-13-InvalidSuperReg.ll
2009-09-20-LiveIntervalsBug.ll
2009-09-21-LiveVariablesBug.ll
2009-09-22-LiveVariablesBug.ll
2009-09-23-LiveVariablesBug.ll
2009-09-24-spill-align.ll
2009-09-27-CoalescerBug.ll
2009-09-28-LdStOptiBug.ll
2009-10-02-NEONSubregsBug.ll
2009-10-16-Scope.ll
2009-10-27-double-align.ll
2009-10-30.ll
2009-11-01-NeonMoves.ll
2009-11-02-NegativeLane.ll
2009-11-07-SubRegAsmPrinting.ll	[ARM] preserve test intent by removing undef	2018-05-17 18:09:56 +00:00
2009-11-13-CoalescerCrash.ll
2009-11-13-ScavengerAssert2.ll
2009-11-13-ScavengerAssert.ll
2009-11-13-VRRewriterCrash.ll
2009-11-30-LiveVariablesBug.ll
2009-12-02-vtrn-undef.ll
2010-03-04-eabi-fp-spill.ll
2010-03-04-stm-undef-addr.ll
2010-03-18-ldm-rtrn.ll
2010-04-09-NeonSelect.ll
2010-04-13-v2f64SplitArg.ll
2010-04-14-SplitVector.ll
2010-04-15-ScavengerDebugValue.ll
2010-05-14-IllegalType.ll
2010-05-17-FastAllocCrash.ll
2010-05-18-LocalAllocCrash.ll
2010-05-18-PostIndexBug.ll
2010-05-19-Shuffles.ll
2010-05-20-NEONSpillCrash.ll
2010-05-21-BuildVector.ll
2010-06-11-vmovdrr-bitcast.ll
2010-06-21-LdStMultipleBug.ll
2010-06-21-nondarwin-tc.ll
2010-06-25-Thumb2ITInvalidIterator.ll
2010-06-29-PartialRedefFastAlloc.ll	[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.	2017-12-07 10:40:31 +00:00
2010-06-29-SubregImpDefs.ll
2010-07-26-GlobalMerge.ll
2010-08-04-EHCrash.ll
2010-08-04-StackVariable.ll
2010-09-21-OptCmpBug.ll
2010-10-25-ifcvt-ldm.ll
2010-11-15-SpillEarlyClobber.ll
2010-11-29-PrologueBug.ll
2010-12-07-PEIBug.ll
2010-12-08-tpsoft.ll
2010-12-15-elf-lcomm.ll
2010-12-17-LocalStackSlotCrash.ll
2011-01-19-MergedGlobalDbg.ll	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
2011-02-04-AntidepMultidef.ll
2011-02-07-AntidepClobber.ll
2011-03-10-DAGCombineCrash.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
2011-03-15-LdStMultipleBug.ll
2011-03-23-PeepholeBug.ll
2011-04-07-schediv.ll
2011-04-11-MachineLICMBug.ll
2011-04-12-AlignBug.ll
2011-04-12-FastRegAlloc.ll
2011-04-15-AndVFlagPeepholeBug.ll
2011-04-15-RegisterCmpPeephole.ll
2011-04-26-SchedTweak.ll
2011-04-27-IfCvtBug.ll
2011-05-04-MultipleLandingPadSuccs.ll
2011-06-09-TailCallByVal.ll
2011-06-16-TailCallByVal.ll
2011-06-29-MergeGlobalsAlign.ll
2011-07-10-GlobalMergeBug.ll
2011-08-02-MergedGlobalDbg.ll	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
2011-08-12-vmovqqqq-pseudo.ll
2011-08-25-ldmia_ret.ll
2011-08-29-ldr_pre_imm.ll
2011-08-29-SchedCycle.ll
2011-09-09-OddVectorDivision.ll
2011-09-19-cpsr.ll
2011-09-28-CMovCombineBug.ll
2011-10-26-ExpandUnalignedLoadCrash.ll
2011-10-26-memset-inline.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
2011-10-26-memset-with-neon.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
2011-11-07-PromoteVectorLoadStore.ll
2011-11-09-BitcastVectorDouble.ll
2011-11-09-IllegalVectorFPIntConvert.ll
2011-11-14-EarlyClobber.ll	[CodeGen] Don't print "pred:" and "opt:" in -debug output	2018-01-09 17:31:07 +00:00
2011-11-28-DAGCombineBug.ll
2011-11-29-128bitArithmetics.ll
2011-11-30-MergeAlignment.ll
2011-12-14-machine-sink.ll
2011-12-19-sjlj-clobber.ll
2012-01-23-PostRA-LICM.ll
2012-01-24-RegSequenceLiveRange.ll
2012-01-26-CoalescerBug.ll
2012-01-26-CopyPropKills.ll
2012-02-01-CoalescerBug.ll
2012-03-05-FPSCR-bug.ll
2012-03-13-DAGCombineBug.ll
2012-03-26-FoldImmBug.ll
2012-04-02-TwoAddrInstrCrash.ll
2012-04-10-DAGCombine.ll
2012-04-24-SplitEHCriticalEdge.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
2012-05-04-vmov.ll
2012-05-10-PreferVMOVtoVDUP32.ll
2012-05-29-TailDupBug.ll
2012-06-12-SchedMemLatency.ll	[CodeGen] Use MIR syntax for MachineMemOperand printing	2018-03-14 21:52:13 +00:00
2012-08-04-DtripleSpillReload.ll
2012-08-08-legalize-unaligned.ll
2012-08-09-neon-extload.ll
2012-08-13-bfi.ll
2012-08-23-legalize-vmull.ll
2012-08-27-CopyPhysRegCrash.ll
2012-08-30-select.ll
2012-09-18-ARMv4ISelBug.ll
2012-09-25-InlineAsmScalarToVectorConv2.ll
2012-09-25-InlineAsmScalarToVectorConv.ll
2012-10-04-AAPCS-byval-align8.ll
2012-10-04-FixedFrame-vs-byval.ll
2012-10-04-LDRB_POST_IMM-Crash.ll
2012-10-18-PR14099-ByvalFrameAddress.ll
2012-11-14-subs_carry.ll
2013-01-21-PR14992.ll
2013-02-27-expand-vfma.ll
2013-04-05-Small-ByVal-Structs-PR15293.ll
2013-04-16-AAPCS-C4-vs-VFP.ll
2013-04-16-AAPCS-C5-vs-VFP.ll
2013-04-18-load-overlap-PR14824.ll
2013-04-21-AAPCS-VA-C.1.cp.ll
2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll
2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll
2013-05-05-IfConvertBug.ll
2013-05-07-ByteLoadSameAddress.ll
2013-05-13-AAPCS-byval-padding2.ll
2013-05-13-AAPCS-byval-padding.ll
2013-05-13-DAGCombiner-undef-mask.ll	DAG: Fix extract_subvector combine for a single element	2018-06-11 21:27:41 +00:00
2013-05-31-char-shift-crash.ll
2013-06-03-ByVal-2Kbytes.ll
2013-07-29-vector-or-combine.ll	[ARM] preserve test intent by removing undef	2018-02-10 15:14:00 +00:00
2013-10-11-select-stalls.ll
2013-11-08-inline-asm-neon-array.ll
2014-01-09-pseudo_expand_implicit_reg.ll	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
2014-02-05-vfp-regs-after-stack.ll
2014-02-21-byval-reg-split-alignment.ll
2014-05-14-DwarfEHCrash.ll
2014-07-18-earlyclobber-str-post.ll
2014-08-04-muls-it.ll
2015-01-21-thumbv4t-ldstr-opt.ll
2016-05-01-RegScavengerAssert.ll
2016-08-24-ARM-LDST-dbginfo-bug.ll	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
2018-02-13-PR36079.ll	[LegalizeDAG] Fix legalization of SETCC	2018-02-16 09:35:16 +00:00
a15-mla.ll
a15-partial-update.ll
a15-SD-dep.ll	[ARM] Add new feature to enable optimizing the VFP registers	2018-07-20 16:49:28 +00:00
a15.ll
aapcs-hfa-code.ll
aapcs-hfa.ll
acle-intrinsics-rot.ll	[ARM] Rotated operand patterns for *xtb16	2018-08-22 12:58:36 +00:00
acle-intrinsics-v5.ll
acle-intrinsics.ll
add-like-or.ll	ARM: convert ORR instructions to ADD where possible on Thumb.	2018-06-20 12:09:44 +00:00
addrmode.ll
addrspacecast.ll
addsubcarry-promotion.ll	[DAG] Promote ADDCARRY / SUBCARRY	2017-12-13 10:45:21 +00:00
adv-copy-opt.ll
aeabi-read-tp.ll
aggregate-padding.ll	[ARM] Fix over-alignment in arguments that are HA of 128-bit vectors	2018-07-30 08:49:30 +00:00
alias_align.ll	[DAGCombine] Fix alignment for offset loads/stores	2018-06-21 08:30:07 +00:00
alias_store.ll	Use .set instead of = when printing assignment in assembly output	2018-03-27 16:44:41 +00:00
aliases.ll	Use .set instead of = when printing assignment in assembly output	2018-03-27 16:44:41 +00:00
align-sp-adjustment.ll
align.ll
alloc-no-stack-realign.ll	[DAGCombine] Disable finding better chains for stores at O0	2017-11-28 04:07:59 +00:00
alloca-align.ll	ARM: use correct offset from base pointer (r6) in call frame regions.	2018-12-07 13:43:55 +00:00
alloca.ll
analyze-branch-bkpt.ll	ARM: Use BKPT instead of TRAP to implement llvm.debugtrap.	2018-10-24 18:10:38 +00:00
and-cmpz.ll	[ARM] Adjust AND immediates to make them cheaper to select.	2018-08-10 21:21:53 +00:00
and-load-combine.ll	[ARM] Add missing pseudo-instruction for Thumb1 RSBS.	2018-10-31 21:45:48 +00:00
apcs-vfp.ll
arg-copy-elide.ll
argaddr.ll
arguments2.ll
arguments3.ll
arguments4.ll
arguments5.ll
arguments6.ll
arguments7.ll
arguments8.ll
arguments_f64_backfill.ll
arguments-nosplit-double.ll
arguments-nosplit-i64.ll
arguments.ll
arm32-round-conv.ll
arm32-rounding.ll
arm-abi-attr.ll
arm-and-tst-peephole.ll	[SchedModel] Fix for read advance cycles with implicit pseudo operands.	2018-10-30 15:04:40 +00:00
arm-asm.ll
arm-eabi.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
arm-frame-lowering-no-terminator.ll
arm-frameaddr.ll
arm-insert-subvector.ll
arm-macho-tail.ll
arm-modifier.ll
arm-negative-stride.ll
arm-position-independence-jump-table.ll	[ARM] Place jump table as the first operand in additions	2017-11-13 11:56:48 +00:00
arm-position-independence.ll
arm-returnaddr.ll
arm-shrink-wrapping-linux.ll	[ARM] Treat cmn immediates as legal in isLegalICmpImmediate.	2018-07-10 23:44:37 +00:00
arm-shrink-wrapping.ll	[SchedModel] Fix for read advance cycles with implicit pseudo operands.	2018-10-30 15:04:40 +00:00
arm-storebytesmerge.ll	[DAGCombine] Improve alias analysis for chain of independent stores.	2018-11-08 19:14:20 +00:00
arm-ttype-target2.ll
arm-vld1.ll	[NEON] Support VLD1xN intrinsics in AArch32 mode (LLVM part)	2018-06-02 16:40:03 +00:00
arm-vlddup-update.ll	[NEON] Fix combining of vldx_dup intrinsics with updating of base addresses	2018-07-05 08:59:49 +00:00
arm-vlddup.ll	[NEON] Support vldNq intrinsics in AArch32 (LLVM part)	2018-06-27 13:57:52 +00:00
arm-vst1.ll	[NEON] Support VST1xN intrinsics in AArch32 mode (LLVM part)	2018-06-10 09:27:27 +00:00
ARMLoadStoreDBG.mir	MachineOperand/MIParser: Do not print debug-use flag, infer it	2018-10-30 23:28:27 +00:00
armv4.ll
armv8.2a-fp16-vector-intrinsics.ll	[ARM] Added FP16 VREV Vector Instrinsic CodeGen support	2018-08-13 08:37:41 +00:00
atomic-64bit.ll
atomic-cmp.ll
atomic-cmpxchg.ll	[ARM] Add missing pseudo-instruction for Thumb1 RSBS.	2018-10-31 21:45:48 +00:00
atomic-load-store.ll
atomic-op.ll	NFC - Various typo fixes in tests	2018-07-04 13:28:39 +00:00
atomic-ops-m33.ll	ARM: use acquire/release instruction variants when available.	2018-12-17 15:05:32 +00:00
atomic-ops-v8.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
atomicrmw_minmax.ll
available_externally.ll
avoid-cpsr-rmw.ll	[SimplifyCFG] Avoid quadratic on a predecessors number behavior in instruction sinking.	2017-12-21 01:22:13 +00:00
bfc.ll
bfi.ll
bfx.ll
bic.ll
bicZext.ll
big-endian-eh-unwind.ll
big-endian-neon-bitconv.ll
big-endian-neon-extend.ll
big-endian-neon-trunc-store.ll
big-endian-ret-f64.ll
big-endian-vector-callee.ll
big-endian-vector-caller.ll
bit-reverse-to-rbit.ll
bits.ll
bool-ext-inc.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
bswap16.ll
bswap-inline-asm.ll
build-attributes-encoding.s
build-attributes-fn-attr0.ll
build-attributes-fn-attr1.ll
build-attributes-fn-attr2.ll
build-attributes-fn-attr3.ll
build-attributes-fn-attr4.ll
build-attributes-fn-attr5.ll
build-attributes-fn-attr6.ll
build-attributes-optimization-minsize.ll
build-attributes-optimization-mixed.ll
build-attributes-optimization-optnone.ll
build-attributes-optimization-optsize.ll
build-attributes-optimization.ll
build-attributes.ll	Recommit of r335326, with the test fixed that I missed.	2018-06-22 10:03:03 +00:00
bx_fold.ll
byval_load_align.ll
byval-align.ll
cache-intrinsic.ll
call_nolink.ll
call-noret-minsize.ll
call-noret.ll
call-tc.ll
call.ll
carry.ll
cbz-implicit-it-range.ll	[ARM] Account for implicit IT when calculating inline asm size	2018-10-08 09:38:28 +00:00
cdp2.ll
cdp.ll
cfi-alignment.ll
clang-section.ll
clz.ll	[ARM] Lower llvm.ctlz.i32 to a libcall when clz is not available.	2018-08-22 21:47:14 +00:00
cmn.ll	[ARM] Make InstrEmitter mark CPSR defs dead for Thumb1.	2018-10-26 19:32:24 +00:00
cmp1-peephole-thumb.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
cmp2-peephole-thumb.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
cmp.ll	ARM: use target-specific SUBS node when combining cmp with cmov.	2018-12-03 11:16:21 +00:00
cmpxchg-idioms.ll
cmpxchg-O0-be.ll
cmpxchg-O0.ll	[ARM] Materialise some boolean values to avoid a branch	2018-02-16 09:23:59 +00:00
cmpxchg-weak.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
cmpxchg.mir	ARMExpandPseudoInsts: Fix CMP_SWAP expansion adding a kill flag to a def	2018-11-02 18:22:15 +00:00
coalesce-dbgvalue.ll	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
coalesce-subregs.ll
code-placement.ll
codemodel.ll	[Targets] Add errors for tiny and kernel codemodel on targets that don't support them	2018-12-07 12:10:23 +00:00
coff-no-dead-strip.ll	test: fix ARM tests harder	2018-01-20 01:26:46 +00:00
combine-movc-sub.ll
combine-vmovdrr.ll
commute-movcc.ll
compare-call.ll
constant-island-crash.ll
constant-island-movwt.mir	[ARM] Avoid injecting constant islands in movw+movt pairs on Windows	2018-08-22 20:34:12 +00:00
constant-islands-cfg.mir	Revert r325754 and r325755 (f16 literal pool) because buildbots were unhappy.	2018-02-22 08:41:55 +00:00
constant-islands.ll
constantfp.ll
constantpool-align.ll
constantpool-promote-dbg.ll	[ARM] Fix correctness checks in promoteToConstantPool.	2018-09-28 20:27:31 +00:00
constantpool-promote-duplicate.ll
constantpool-promote-ldrh.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
constantpool-promote.ll	[ARM] Fix correctness checks in promoteToConstantPool.	2018-09-28 20:27:31 +00:00
constants.ll
copy-by-struct-i32.ll	[ARM] Set Defs = [CPSR] for COPY_STRUCT_BYVAL, as it clobbers CPSR.	2018-12-21 18:07:10 +00:00
copy-cpsr.ll
copy-paired-reg.ll
cortex-a57-misched-alu.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
cortex-a57-misched-basic.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
cortex-a57-misched-ldm-wrback.ll	[SchedModel] Fix for read advance cycles with implicit pseudo operands.	2018-10-30 15:04:40 +00:00
cortex-a57-misched-ldm.ll	[SchedModel] Fix for read advance cycles with implicit pseudo operands.	2018-10-30 15:04:40 +00:00
cortex-a57-misched-stm-wrback.ll
cortex-a57-misched-stm.ll
cortex-a57-misched-vadd.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
cortex-a57-misched-vfma.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
cortex-a57-misched-vldm-wrback.ll	[SchedModel] Fix for read advance cycles with implicit pseudo operands.	2018-10-30 15:04:40 +00:00
cortex-a57-misched-vldm.ll	[SchedModel] Fix for read advance cycles with implicit pseudo operands.	2018-10-30 15:04:40 +00:00
cortex-a57-misched-vstm-wrback.ll
cortex-a57-misched-vstm.ll
cortex-a57-misched-vsub.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
cortexr52-misched-basic.ll	[ARM] Enable misched for R52.	2018-04-27 11:29:49 +00:00
crash-greedy-v6.ll
crash-greedy.ll	[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.	2017-12-07 10:40:31 +00:00
crash-O0.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
crash-on-pow2-shufflevector.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
crash-shufflevector.ll
crash.ll
crc32.ll
cse-call.ll
cse-flags.ll
cse-ldrlit.ll
cse-libcalls.ll
ctor_order.ll
ctors_dtors.ll
cttz_vector.ll	[ARM] Regenerate cttz tests	2018-10-14 16:49:04 +00:00
cttz.ll
cxx-tlscc.ll
dag-combine-ldst.ll
dagcombine-anyexttozeroext.ll	[DAGCombiner] Add a combine to turn a build vector of zero extends of extract vector elts into a vector zero extend and possibly an extract subvector.	2018-04-07 19:09:50 +00:00
dagcombine-concatvector.ll
darwin-eabi.ll	ARM: switch armv7em MachO triple to hard-float defaults and libcalls.	2018-07-19 12:44:51 +00:00
darwin-tls-preserved.ll
darwin-tls.ll
data-in-code-annotations.ll
dbg-range-extension.mir	MachineOperand/MIParser: Do not print debug-use flag, infer it	2018-10-30 23:28:27 +00:00
dbg.ll
DbgValueOtherTargets.test
debug-frame-large-stack.ll	Partial revert of "NFC - Various typo fixes in tests"	2018-07-05 08:42:16 +00:00
debug-frame-no-debug.ll
debug-frame-vararg.ll	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
debug-frame.ll	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
debug-info-arg.ll	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
debug-info-blocks.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
debug-info-branch-folding.ll	[ARM] preserve test intent by removing undef	2018-05-16 21:57:00 +00:00
debug-info-d16-reg.ll	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
debug-info-no-frame.ll	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
debug-info-qreg.ll	[ARM] make test immune to scalarization improvements; NFC	2018-12-14 18:47:04 +00:00
debug-info-s16-reg.ll	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
debug-info-sreg2.ll	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
debug-segmented-stacks.ll	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
debugtrap.ll	ARM: Use BKPT instead of TRAP to implement llvm.debugtrap.	2018-10-24 18:10:38 +00:00
default-float-abi.ll
default-reloc.ll
demanded-bits-and.ll	[ARM] Handle all-ones mask explicitly in targetShrinkDemandedConstant.	2018-08-22 20:13:45 +00:00
deprecated-asm.s	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
deps-fix.ll	Separate ExecutionDepsFix into 4 parts:	2018-01-22 10:05:23 +00:00
disable-fp-elim.ll
disable-tail-calls.ll
div.ll
divmod-eabi.ll
divmod-hwdiv.ll
divmod.ll
domain-conv-vmovs.ll
dsp-mlal.ll	[ARM] Add codegen for SMMULR, SMMLAR and SMMLSR	2018-01-12 09:24:41 +00:00
dwarf-eh.ll	Emit smaller exception tables for non-SJLJ mode.	2018-02-09 17:13:37 +00:00
dwarf-unwind.ll
dyn-stackalloc.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
early-cfi-sections.ll	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
eh-dispcont.ll
eh-resume-darwin.ll
ehabi-filters.ll
ehabi-handlerdata-nounwind.ll	Emit smaller exception tables for non-SJLJ mode.	2018-02-09 17:13:37 +00:00
ehabi-handlerdata.ll	Emit smaller exception tables for non-SJLJ mode.	2018-02-09 17:13:37 +00:00
ehabi-no-landingpad.ll
ehabi-unwind.ll
ehabi.ll	[ARM] Use dwarf exception handling on MinGW	2017-11-17 08:04:40 +00:00
elf-lcomm-align.ll
emit-big-cst.ll
emutls1.ll
emutls_generic.ll	[MinGW] [ARM] Add stubs for potential automatic dllimported variables	2018-08-31 08:00:25 +00:00
emutls.ll	[TLS] use emulated TLS if the target supports only this mode	2018-02-28 17:48:55 +00:00
execute-only-big-stack-frame.ll	[ARM] Allow execute only code on Cortex-m23	2018-09-28 08:55:19 +00:00
execute-only-section.ll	[ARM] Allow execute only code on Cortex-m23	2018-09-28 08:55:19 +00:00
execute-only.ll	[ARM] Allow execute only code on Cortex-m23	2018-09-28 08:55:19 +00:00
expand-pseudos.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
extload-knownzero.ll
extloadi1.ll
fabs-neon.ll
fabs-to-bfc.ll
fabss.ll
fadds.ll
fast-isel-align.ll	Relax fast register allocator related test cases; NFC	2018-10-29 20:10:42 +00:00
fast-isel-binary.ll
fast-isel-br-const.ll
fast-isel-br-phi.ll
fast-isel-call-multi-reg-return.ll
fast-isel-call.ll	[FastISel] Disable local value sinking by default	2018-04-11 16:03:07 +00:00
fast-isel-cmp-imm.ll
fast-isel-conversion.ll
fast-isel-crash2.ll
fast-isel-crash.ll
fast-isel-deadcode.ll
fast-isel-ext.ll
fast-isel-fold.ll
fast-isel-frameaddr.ll
fast-isel-GEP-coalesce.ll
fast-isel-icmp.ll
fast-isel-indirectbr.ll
fast-isel-inline-asm.ll
fast-isel-intrinsic.ll	[FastISel] Disable local value sinking by default	2018-04-11 16:03:07 +00:00
fast-isel-ldr-str-arm.ll
fast-isel-ldr-str-thumb-neg-index.ll
fast-isel-ldrh-strh-arm.ll	Relax fast register allocator related test cases; NFC	2018-10-29 20:10:42 +00:00
fast-isel-load-store-verify.ll
fast-isel-mvn.ll
fast-isel-pic.ll
fast-isel-pie.ll
fast-isel-pred.ll
fast-isel-redefinition.ll
fast-isel-remat-same-constant.ll
fast-isel-ret.ll
fast-isel-select.ll	[FastISel] Disable local value sinking by default	2018-04-11 16:03:07 +00:00
fast-isel-shift-materialize.ll	MachO: trap unreachable instructions	2018-04-13 22:25:20 +00:00
fast-isel-shifter.ll
fast-isel-static.ll
fast-isel-update-valuemap-for-extract.ll
fast-isel-vaddd.ll
fast-isel-vararg.ll	[FastISel] Disable local value sinking by default	2018-04-11 16:03:07 +00:00
fast-isel.ll	Relax fast register allocator related test cases; NFC	2018-10-29 20:10:42 +00:00
fast-tail-call.ll
fastcc-vfp.ll
fastisel-gep-promote-before-add.ll
fastisel-thumb-litpool.ll
fcmp-xo.ll	[ARM] Support float literals under XO	2018-03-28 10:02:26 +00:00
fcopysign.ll
fdivs.ll
fence-singlethread.ll
fixunsdfdi.ll
flag-crash.ll
float-helpers.s	[ARM][NFC] codegen tests cleanup: remove dangling check prefixes	2018-11-23 10:08:39 +00:00
floorf.ll
fmacs.ll	[ARM][NFCI] Do not fuse VADD and VMUL, continued (1/2)	2018-10-17 07:26:35 +00:00
fmdrr-fmrrd.ll
fmscs.ll
fmuls.ll
fnattr-trap.ll
fnegs.ll
fnmacs.ll
fnmscs.ll	[ARM] Add missing selection patterns for vnmla	2017-09-22 09:50:52 +00:00
fnmul.ll	easing the constraint for isNegatibleForFree and GetNegatedExpression	2018-06-14 20:54:13 +00:00
fnmuls.ll
fold-const.ll
fold-sext-sextload.ll	[ARM][NFC] Make tests immune to better div optimizations	2018-10-30 22:08:13 +00:00
fold-stack-adjust.ll
fold-zext-zextload.ll	[ARM][NFC] Make tests immune to better div optimizations	2018-10-30 22:08:13 +00:00
formal.ll
fp16-args.ll
fp16-instructions.ll	[SchedModel] Fix for read advance cycles with implicit pseudo operands.	2018-10-30 15:04:40 +00:00
fp16-intrinsic-vector-1op.ll	[ARM] Support for v4f16 and v8f16 vectors	2018-03-19 13:35:25 +00:00
fp16-intrinsic-vector-2op.ll	[ARM] Support for v4f16 and v8f16 vectors	2018-03-19 13:35:25 +00:00
fp16-litpool2-arm.mir	[MIR] Add support for debug metadata for fixed stack objects	2018-04-25 18:58:06 +00:00
fp16-litpool3-arm.mir	[MIR] Add support for debug metadata for fixed stack objects	2018-04-25 18:58:06 +00:00
fp16-litpool-arm.mir	Recommit: [ARM] f16 constant pool fix	2018-02-22 10:43:57 +00:00
fp16-litpool-thumb.mir	Recommit: [ARM] f16 constant pool fix	2018-02-22 10:43:57 +00:00
fp16-promote.ll	[NFC] Rename minnan and maxnan to minimum and maximum	2018-10-24 22:49:55 +00:00
fp16-v3.ll
fp16-vld.ll	[ARM] FP16: support vld1.16 for vector loads with post-increment	2018-12-03 08:26:34 +00:00
fp16-vminmaxnm-safe.ll	[ARM] FP16 vmaxnm/vminnm scalar instructions	2018-04-13 15:34:26 +00:00
fp16-vminmaxnm-vector.ll	[ARM] FP16: support the vector vmin and vmax variants	2018-08-08 07:20:15 +00:00
fp16-vminmaxnm.ll	[ARM] FP16 vmaxnm/vminnm scalar instructions	2018-04-13 15:34:26 +00:00
fp16.ll	NFC - Various typo fixes in tests	2018-07-04 13:28:39 +00:00
fp_convert.ll
fp-arg-shuffle.ll
fp-fast.ll
fp-only-sp.ll
fp.ll
fparith.ll
fpcmp_ueq.ll
fpcmp-f64-neon-opt.ll
fpcmp-opt.ll
fpcmp.ll
fpconsts.ll
fpconv.ll	[ARM] Tighten f64<->f16 conversion requirements	2018-09-12 16:24:43 +00:00
fpmem.ll
fpoffset_overflow.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
fpow.ll
fpowi.ll
fpscr-intrinsics.ll
fptoint.ll
fpvcvtr.ll	[ARM] Add LLVM tests for the vcvtr builtins	2018-02-17 19:59:29 +00:00
frame-register.ll
fsubs.ll
ftrunc.ll	[DAGCombine] (float)((int) f) --> ftrunc (PR36617)	2018-04-20 15:07:55 +00:00
func-argpassing-endian.ll	[DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_VECTOR_ELT	2018-07-17 09:45:35 +00:00
fusedMAC.ll	[ARM] Do not fuse VADD and VMUL, continued (2/2)	2018-10-17 10:05:44 +00:00
gep-optimization.ll
ghc-tcreturn-lowered.ll
global-merge-1.ll	[GlobalMerge] Set the alignment on merged global structs	2018-06-06 14:48:32 +00:00
global-merge-addrspace.ll
global-merge-alignment.ll	[GlobalMerge] Set the alignment on merged global structs	2018-06-06 14:48:32 +00:00
global-merge-dllexport.ll	Use .set instead of = when printing assignment in assembly output	2018-03-27 16:44:41 +00:00
global-merge-external-2.ll	[GlobalMerge] Fix GlobalMerge on bss external global variables.	2018-08-30 00:49:50 +00:00
global-merge-external.ll	Use .set instead of = when printing assignment in assembly output	2018-03-27 16:44:41 +00:00
global-merge.ll	[GlobalMerge] Exit early if only one global is to be merged	2018-05-19 18:00:02 +00:00
globals.ll
gpr-paired-spill-thumbinst.ll
gpr-paired-spill.ll
gv-stubs-crash.ll
half.ll	[ARM] Tighten f64<->f16 conversion requirements	2018-09-12 16:24:43 +00:00
hardfloat_neon.ll
hello.ll
hfa-in-contiguous-registers.ll
hidden-vis-2.ll
hidden-vis-3.ll
hidden-vis.ll
hints.ll
i1.ll
iabs.ll
ifconv-kills.ll
ifconv-regmask.ll
ifcvt1.ll
ifcvt2.ll
ifcvt3.ll
ifcvt4.ll
ifcvt5.ll
ifcvt6.ll
ifcvt7.ll
ifcvt8.ll
ifcvt9.ll
ifcvt10.ll	[ARM] preserve test intent by removing undef	2018-05-16 22:20:33 +00:00
ifcvt11.ll
ifcvt12.ll
ifcvt_canFallThroughTo.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
ifcvt_diamond_unanalyzable.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
ifcvt_forked_diamond_unanalyzable.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
ifcvt_simple_bad_zero_prob_succ.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
ifcvt_simple_unanalyzable.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
ifcvt_triangleWoCvtToNextEdge.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
ifcvt-branch-weight-bug.ll	[CodeGen] Unify the syntax of MBB successors in MIR and -debug output	2018-02-09 00:10:31 +00:00
ifcvt-branch-weight.ll	[CodeGen] Unify the syntax of MBB successors in MIR and -debug output	2018-02-09 00:10:31 +00:00
ifcvt-callback.ll
ifcvt-dead-def.ll	[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.	2017-12-07 10:40:31 +00:00
ifcvt-iter-indbr.ll	[CodeGen] Unify the syntax of MBB successors in MIR and -debug output	2018-02-09 00:10:31 +00:00
ifcvt-regmask-noreturn.ll
illegal-bitfield-loadstore.ll	[ARM] Adjust AND immediates to make them cheaper to select.	2018-08-10 21:21:53 +00:00
illegal-vector-bitcast.ll
imm-peephole-arm.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
imm-peephole-thumb.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
imm.ll
immcost.ll
indirect-hidden.ll	[CodeGen] Always use printReg to print registers in both MIR and debug	2017-11-30 16:12:24 +00:00
indirect-reg-input.ll
indirectbr-2.ll
indirectbr-3.ll
indirectbr.ll	Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.	2018-06-20 22:01:04 +00:00
inline-asm-clobber.ll	[CodeGen] emit inline asm clobber list warnings for reserved (cont)	2018-08-30 12:52:35 +00:00
inline-diagnostics.ll
inlineasm2.ll
inlineasm3.ll
inlineasm4.ll
inlineasm-64bit.ll	Fix uninitialized read in ARM's PrintAsmOperand	2018-07-30 16:45:40 +00:00
inlineasm-error-t-toofewregs.ll	[ARM] Fix redirect in inline assembly test	2018-02-15 19:17:55 +00:00
inlineasm-global.ll
inlineasm-imm-arm.ll
inlineasm-imm-thumb2.ll
inlineasm-imm-thumb.ll
inlineasm-ldr-pseudo.ll
inlineasm-operand-implicit-cast.ll	Support inline asm with multiple 64bit output in 32bit GPR	2018-08-08 09:35:26 +00:00
inlineasm-switch-mode-oneway-from-arm.ll
inlineasm-switch-mode-oneway-from-thumb.ll
inlineasm-switch-mode.ll
inlineasm-X-allocation.ll	[ARM][NFC] Fix test inlineasm-X-allocation.ll	2018-10-29 08:45:56 +00:00
inlineasm-X-constraint.ll
inlineasm.ll	[ARM] Allow 64- and 128-bit types with 't' inline asm constraint	2018-02-15 14:44:22 +00:00
insn-sched1.ll
int-to-fp.ll
integer_insertelement.ll
interrupt-attr.ll
interval-update-remat.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
interwork.ll
intrinsics-coprocessor.ll
intrinsics-crypto.ll
intrinsics-memory-barrier.ll
intrinsics-overflow.ll	[ARM] Make InstrEmitter mark CPSR defs dead for Thumb1.	2018-10-26 19:32:24 +00:00
intrinsics-v8.ll
invalid-target.ll	[ADT] Normalize empty triple components	2018-08-08 22:23:57 +00:00
invalidated-save-point.ll
invoke-donothing-assert.ll
isel-v8i32-crash.ll
ispositive.ll
jump-table-islands-split.ll
jump-table-islands.ll
jump-table-tbh.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
jumptable-label.ll
krait-cpu-div-attribute.ll
large-stack.ll
large-vector.ll	ARM: don't try to over-align large vectors as arguments.	2018-05-03 12:54:25 +00:00
ldaex-stlex.ll
ldc2l.ll
ldm-base-writeback.ll
ldm-stm-base-materialization.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
ldm-stm-i256.ll
ldm.ll
ldr_ext.ll
ldr_frame.ll
ldr_post.ll
ldr_pre.ll
ldr.ll
ldrcppic.ll	[ARM] Add MemOperand to LDRcp to enable DCE.	2018-11-09 23:09:17 +00:00
ldrd-memoper.ll	[CodeGen] Use MIR syntax for MachineMemOperand printing	2018-03-14 21:52:13 +00:00
ldrd.ll	[ARM][NFC] codegen tests cleanup: remove dangling check prefixes	2018-11-23 10:08:39 +00:00
ldrex-frame-size.ll	ARM: fix Thumb2 CodeGen for ldrex with folded frame-index.	2018-09-07 09:21:25 +00:00
ldst-f32-2-i32.ll
ldstrex-m.ll	ARM: use acquire/release instruction variants when available.	2018-12-17 15:05:32 +00:00
ldstrex.ll	ARM: fix Thumb2 CodeGen for ldrex with folded frame-index.	2018-09-07 09:21:25 +00:00
legalize-unaligned-load.ll
lit.local.cfg
litpool-licm.ll	[CodeGen] Always use printReg to print registers in both MIR and debug	2017-11-30 16:12:24 +00:00
load_i1_select.ll	[ARM] Allow CMPZ transforms even if the input has multiple uses.	2018-06-08 21:16:56 +00:00
load_store_multiple.ll	[ARM] Fix isRenamable flag setting on expanded VSTMDIA opcode.	2017-12-14 18:06:25 +00:00
load_store_opt_clobber_cpsr.mir	[CodeGen] Fix forward scan in MachineBasicBlock::computeRegisterLiveness.	2018-11-14 00:39:29 +00:00
load_store_opt_kill.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
load_store_opt_reg_limit.mir	[ARM][ARMLoadStoreOptimizer]	2018-09-24 10:42:22 +00:00
load-address-masked.ll
load-arm.ll
load-combine-big-endian.ll	Fix a reoccuring typo in load-combine tests	2018-03-27 17:33:50 +00:00
load-combine.ll	Fix a reoccuring typo in load-combine tests	2018-03-27 17:33:50 +00:00
load-global2.ll	[arm] Fix Unnecessary reloads from GOT.	2017-11-13 20:45:38 +00:00
load-global.ll
load-store-flags.ll
load.ll
local-call.ll	[CodeGen] Always use printReg to print registers in both MIR and debug	2017-11-30 16:12:24 +00:00
log2_not_readnone.ll
long_shift.ll
long-setcc.ll	[ARM] Materialise some boolean values to avoid a branch	2018-02-16 09:23:59 +00:00
long.ll
longMAC.ll	[ARM] Return true in enableMultipleCopyHints().	2018-02-16 09:51:01 +00:00
loop-align-cortex-m.ll	ARM: align loops to 4 bytes on Cortex-M3 and Cortex-M4.	2018-09-13 10:28:05 +00:00
loopvectorize_pr33804.ll
lowerMUL-newload.ll
lsr-code-insertion.ll
lsr-icmp-imm.ll
lsr-scale-addr-mode.ll
lsr-unfolded-offset.ll
machine-copyprop.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
machine-cse-cmp.ll	[DAGCombiner] Teach DAG combiner that A-(B-C) can be folded to A+(C-B)	2018-07-28 00:27:25 +00:00
machine-licm.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
macho-embedded-float.ll	ARM: switch armv7em MachO triple to hard-float defaults and libcalls.	2018-07-19 12:44:51 +00:00
macho-extern-hidden.ll
macho-frame-offset.ll
MachO-subtypes.ll
macho-trap.ll	MachO: trap unreachable instructions	2018-04-13 22:25:20 +00:00
mature-mc-support.ll
mem.ll
memcpy-inline.ll	[CodeGen] Allow mempcy/memset to generate small overlapping stores.	2018-12-13 09:56:19 +00:00
memcpy-ldm-stm.ll	[CodeGen] Allow mempcy/memset to generate small overlapping stores.	2018-12-13 09:56:19 +00:00
memcpy-no-inline.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
memfunc.ll	[IR] Allow increasing the alignment of dso-local globals.	2018-10-31 23:03:58 +00:00
memset-inline.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
MergeConsecutiveStores.ll
metadata-default.ll
metadata-short-enums.ll
metadata-short-wchar.ll
minmax.ll
minsize-call-cse.ll
minsize-imms.ll
minsize-litpools.ll
misched-copy-arm.ll	[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.	2017-12-07 10:40:31 +00:00
misched-fp-basic.ll
misched-fusion-aes.ll	[DAGCombine] Improve alias analysis for chain of independent stores.	2018-11-08 19:14:20 +00:00
misched-fusion-lit.ll	[ARM] Add new target feature to fuse literal generation	2018-07-27 18:16:47 +00:00
misched-int-basic-thumb2.mir	[CodeGen] Always print register ties in MI::dump()	2018-09-26 13:33:09 +00:00
misched-int-basic.mir	[CodeGen] Always print register ties in MI::dump()	2018-09-26 13:33:09 +00:00
mls.ll
movcc-double.ll
movt-movw-global.ll
movt.ll
msr-it-block.ll
mul_const.ll
mul.ll
mulhi.ll
mult-alt-generic-arm.ll
mvn.ll
named-reg-alloc.ll
named-reg-notareg.ll
negate-i1.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
negative-offset.ll
neon_arith1.ll
neon_cmp.ll
neon_div.ll
neon_fpconv.ll
neon_ld1.ll
neon_ld2.ll
neon_minmax.ll
neon_shift.ll
neon_spill.ll
neon_vabs.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
neon_vshl_minint.ll
neon-dot-product.ll	[ARM] Codegen for v8.2A dot product intrinsics	2018-04-27 12:50:40 +00:00
neon-fma.ll
neon-spfp.ll
neon-v8.1a.ll
nest-register.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
no_redundant_trunc_for_cmp.ll
no-arm-mode.ll
no-cfi.ll
no-cmov2bfi.ll
no-fpscr-liveness.ll
no-fpu.ll
no-tail-call.ll
none-macho-v4t.ll
none-macho.ll
nonreserved-callframe-with-basereg.mir	ARM: use correct offset from base pointer (r6) in call frame regions.	2018-12-07 13:43:55 +00:00
noopt-dmb-v7.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
nop_concat_vectors.ll
noreturn-csr-skip.mir	Reapply ARM: Do not spill CSR to stack on entry to noreturn functions	2018-04-07 10:57:03 +00:00
noreturn.ll
null-streamer.ll
opt-shuff-tstore.ll
optimize-dmbs-v7.ll
optselect-regclass.ll
out-of-registers.ll
overflow-intrinsic-optimizations.ll	[ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m.	2018-07-02 21:05:26 +00:00
pack.ll
peephole-bitcast.ll
peephole-phi.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
pei-swiftself.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
phi.ll
pic.ll
pie.ll
plt-relative-reloc.ll
popcnt.ll	[ARM][NEON] Improve vector popcnt lowering with PADDL (PR39281)	2018-10-15 13:20:41 +00:00
pow.ll	[DAGCombiner] try to convert pow(x, 0.25) to sqrt(sqrt(x))	2018-09-05 17:01:56 +00:00
pr3502.ll
pr13249.ll
pr18364-movw.ll
pr25317.ll	[CodeGen] Always use printReg to print registers in both MIR and debug	2017-11-30 16:12:24 +00:00
pr25838.ll	[LivePhysRegs] Fix handling of return instructions.	2018-02-06 23:00:17 +00:00
pr26669.ll
pr32545.ll
pr32578.ll	ARM: Fix PR32578	2017-11-28 01:17:52 +00:00
pr34045-2.ll	[ARM] Use ADDCARRY / SUBCARRY	2017-12-11 12:13:45 +00:00
pr34045.ll	[ARM] Use ADDCARRY / SUBCARRY	2017-12-11 12:13:45 +00:00
pr35103.ll	[ARM] Use ADDCARRY / SUBCARRY	2017-12-11 12:13:45 +00:00
pr36577.ll	[DAGCombiner] form 'not' ops ahead of shifts (PR39657)	2018-11-22 19:24:10 +00:00
pr39060.ll	[ARM] Fix for PR39060	2018-09-26 10:56:00 +00:00
pr39571.ll	[DAGCombiner] Fix load-store forwarding of indexed loads.	2018-11-12 14:05:40 +00:00
PR15053.ll
PR32721_ifcvt_triangle_unanalyzable.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
PR35379.ll	[ARM] Fix PR35379 - incorrect unwind information when compiling with -Oz	2018-01-08 14:47:19 +00:00
preferred-align.ll	[CodeGen] Always use printReg to print registers in both MIR and debug	2017-11-30 16:12:24 +00:00
prefetch.ll
prera-ldst-aliasing.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
prera-ldst-insertpt.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
print-memb-operand.ll
print-registers.ll	Fix "Q" and "R" inline assembly template modifiers for big-endian Arm	2018-08-30 10:28:23 +00:00
private.ll
rbit.ll
readcyclecounter.ll
readonly-aliases.ll	ARM: handle checking aliases with out-of-bounds GEPs	2018-10-24 00:00:52 +00:00
readtp.ll
reg_sequence.ll	[ARM] preserve test intent by removing undef	2018-05-17 18:08:27 +00:00
regpair_hint_phys.ll
relax-per-target-feature.ll	[MC] Pass MCSubtargetInfo to fixupNeedsRelaxation and applyFixup	2018-06-06 09:40:06 +00:00
rem_crash.ll
ret0.ll
ret_arg1.ll
ret_arg2.ll
ret_arg3.ll
ret_arg4.ll
ret_arg5.ll
ret_f32_arg2.ll
ret_f32_arg5.ll
ret_f64_arg2.ll
ret_f64_arg_reg_split.ll
ret_f64_arg_split.ll
ret_f64_arg_stack.ll
ret_i64_arg2.ll
ret_i64_arg3.ll
ret_i64_arg_split.ll
ret_i128_arg2.ll
ret_sret_vector.ll
ret_void.ll
returned-ext.ll
returned-trunc-tail-calls.ll
rev.ll
ror.ll
rotate.ll
sat-to-bitop.ll	[ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations	2018-02-28 17:13:07 +00:00
saxpy10-a9.ll
sbfx.ll
scavenging.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
sched-it-debug-nodes.mir	MachineOperand/MIParser: Do not print debug-use flag, infer it	2018-10-30 23:28:27 +00:00
sdiv-pow2-arm-size.ll	[ARM] Don't expand sdiv when optimising for minsize	2018-11-30 08:14:28 +00:00
sdiv-pow2-thumb-size.ll	[ARM] Don't expand sdiv when optimising for minsize	2018-11-30 08:14:28 +00:00
section-name.ll
section.ll
segmented-stacks-dynamic.ll
segmented-stacks.ll	[X86,ARM] Retain split-stack prolog check for sibling calls	2018-06-26 14:11:30 +00:00
select_const.ll	[ARM] Adjust AND immediates to make them cheaper to select.	2018-08-10 21:21:53 +00:00
select_xform.ll	[ARM] Return true in enableMultipleCopyHints().	2018-02-16 09:51:01 +00:00
select-imm.ll	[ARM] Add missing pseudo-instruction for Thumb1 RSBS.	2018-10-31 21:45:48 +00:00
select-undef.ll
select.ll	ARM: use target-specific SUBS node when combining cmp with cmov.	2018-12-03 11:16:21 +00:00
setcc-logic.ll	[DAGCombiner] allow hoisting vector bitwise logic ahead of truncates	2018-12-16 14:57:04 +00:00
setcc-type-mismatch.ll
setjmp_longjmp.ll	[ARM] Restore the right frame pointer register in Int_eh_sjlj_longjmp	2017-09-28 19:04:30 +00:00
shift-combine.ll	NFC - Various typo fixes in tests	2018-07-04 13:28:39 +00:00
shift-i64.ll	[ARM] Expand long shifts for Thumb1 to __aeabi_ calls	2018-01-24 18:00:57 +00:00
shifter_operand.ll
shuffle.ll
sincos.ll	[TargetLowering] Android has sincos functions	2018-09-18 13:18:21 +00:00
single-issue-r52.mir	[CodeGen] Use MIR syntax for MachineMemOperand printing	2018-03-14 21:52:13 +00:00
sjlj-prepare-critical-edge.ll
sjljeh-swifterror.ll	SjLjEHPrepare: Don't reg-to-mem swifterror values	2018-03-14 15:44:07 +00:00
sjljehprepare-lower-empty-struct.ll	[ARM] Fix SJLJ exception handling when manually chosen on a platform where it isn't default	2017-09-28 19:04:14 +00:00
smlad0.ll	[ARM] Prevent parallel macs for unsigned values	2018-11-26 10:22:55 +00:00
smlad1.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smlad2.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smlad3.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smlad4.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smlad5.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smlad6.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smlad7.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smlad8.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smlad9.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smlad10.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smlad11.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smlad12.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smladx-1.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smlald0.ll	[ARM] Prevent parallel macs for unsigned values	2018-11-26 10:22:55 +00:00
smlald1.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smlald2.ll	[ARM] Prevent parallel macs for unsigned values	2018-11-26 10:22:55 +00:00
smlaldx-1.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smlaldx-2.ll	Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")	2018-10-18 19:34:30 +00:00
smml.ll	[ARM][NFC] codegen tests cleanup: remove dangling check prefixes	2018-11-23 10:08:39 +00:00
smul.ll
softfp-fabs-fneg.ll	[ARM][NFC] codegen tests cleanup: remove dangling check prefixes	2018-11-23 10:08:39 +00:00
space-directive.ll
special-reg-acore.ll
special-reg-mcore.ll
special-reg-v8m-base.ll
special-reg-v8m-main.ll
special-reg.ll
spill-q.ll	[ARM] preserve test intent by removing undef	2018-05-16 22:20:11 +00:00
splitkit.ll	SplitKit: Fix liveness recomputation in some remat cases.	2018-02-02 00:08:19 +00:00
ssat-lower.ll
ssat-upper.ll
ssat-v4t.ll
ssat.ll
ssp-data-layout.ll
stack_guard_remat.ll
stack-alignment.ll
stack-frame.ll
stack-protector-bmovpcb_call.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
stack-size-section.ll	Recommit r335333 "[MC] - Add .stack_size sections into groups and link them with .text"	2018-06-22 10:53:47 +00:00
stackpointer.ll
static-addr-hoisting.ll
stc2.ll
stm.ll
str_post.ll
str_pre-2.ll
str_pre.ll
str_trunc.ll
struct_byval_arm_t1_t2.ll	[ARM] Return true in enableMultipleCopyHints().	2018-02-16 09:51:01 +00:00
struct_byval.ll
struct-byval-frame-index.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
sub-cmp-peephole.ll	DAG combiner: fold (select, C, X, undef) -> X	2018-11-16 23:13:38 +00:00
sub.ll
subreg-remat.ll	[CodeGen] Don't print "pred:" and "opt:" in -debug output	2018-01-09 17:31:07 +00:00
subtarget-features-long-calls.ll
subtarget-no-movt.ll
swift-atomics.ll
swift-ios.ll
swift-return.ll
swift-vldm.ll
swifterror.ll	[FastISel] Disable local value sinking by default	2018-04-11 16:03:07 +00:00
swiftself.ll
switch-minsize.ll
sxt_rot.ll
t2-imm.ll
t2-shrink-ldrpost.ll
t2abs-killflags.ll
tail-call-builtin.ll
tail-call-float.ll
tail-call-weak.ll
tail-call.ll	[CodeGen] Enable tail calls for functions with NonNull attributes.	2018-09-26 10:46:18 +00:00
tail-dup-bundle.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
tail-dup-kill-flags.ll
tail-dup.ll
tail-merge-branch-weight.ll	[CodeGen] Unify the syntax of MBB successors in MIR and -debug output	2018-02-09 00:10:31 +00:00
tail-opts.ll
tailcall-mem-intrinsics.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
taildup-branch-weight.ll	[CodeGen] Unify the syntax of MBB successors in MIR and -debug output	2018-02-09 00:10:31 +00:00
test-sharedidx.ll
this-return.ll
thread_pointer.ll
thumb1_return_sequence.ll	[ARM] Fix an off-by-one error when restoring LR for 16-bit Thumb	2017-11-27 10:13:14 +00:00
thumb1-div.ll
thumb1-ldst-opt.ll	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
thumb1-varalloc.ll
thumb2-it-block.ll
thumb2-size-opt.ll
thumb2-size-reduction-internal-flags.ll
thumb_indirect_calls.ll
thumb-alignment.ll
thumb-big-stack.ll
thumb-litpool.ll	[CodeGen] Always use printReg to print registers in both MIR and debug	2017-11-30 16:12:24 +00:00
thumb-stub.ll
tls1.ll
tls2.ll
tls3.ll
tls-models.ll	[ARM][NFC] codegen tests cleanup: remove dangling check prefixes	2018-11-23 10:08:39 +00:00
trap-unreachable.ll	[CodeGen] Add a -trap-unreachable option for debugging	2018-02-12 11:06:27 +00:00
trap.ll	ARM: Use BKPT instead of TRAP to implement llvm.debugtrap.	2018-10-24 18:10:38 +00:00
trunc_ldr.ll
truncstore-dag-combine.ll
tst_teq.ll
twoaddrinstr.ll	[SchedModel] Fix for read advance cycles with implicit pseudo operands.	2018-10-30 15:04:40 +00:00
uint64tof64.ll
umulo-32.ll	[ARM] make test immune to improvements in undef simplification	2018-11-18 16:49:42 +00:00
umulo-64-legalisation-lowering.ll	[SelectionDAG] Improve the legalisation lowering of UMULO.	2018-08-16 18:39:39 +00:00
umulo-128-legalisation-lowering.ll	[SelectionDAG] Improve the legalisation lowering of UMULO.	2018-08-16 18:39:39 +00:00
unaligned_load_store_vector.ll	ARM: be conservative when asked load/store alignment of weird type.	2018-05-21 12:43:54 +00:00
unaligned_load_store_vfp.ll
unaligned_load_store.ll
undef-sext.ll
undefined.ll
unfold-shifts.ll	[ARM] and, or, xor and add with shl combine	2017-11-02 10:43:10 +00:00
unord.ll
unsafe-fsub.ll
unschedule-first-call.ll
unwind-fp.ll	[ARM] Fix unwind information for floating point registers	2018-09-19 13:25:31 +00:00
unwind-init.ll
urem-opt-size.ll
usat-lower.ll
usat-upper.ll
usat-v4t.ll
usat.ll	[ARM] Lower unsigned saturation to USAT	2017-12-20 11:13:57 +00:00
useaa.ll	[ARM] Enable useAA() for the in-order Cortex-R52	2018-06-21 15:48:29 +00:00
uxt_rot.ll
uxtb.ll
v1-constant-fold.ll
v6-jumptable-clobber.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
v6m-smul-with-overflow.ll
v6m-umul-with-overflow.ll
v7k-abi-align.ll
v7k-libcalls.ll
v7k-sincos.ll
v8m-tail-call.ll	[ARM] Avoid spilling lr with Thumb1 tail calls.	2018-08-08 20:03:10 +00:00
v8m.base-jumptable_alignment.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
va_arg.ll
vaba.ll
vabd.ll
vabs.ll
vadd.ll
vararg_no_start.ll
varargs-spill-stack-align-nacl.ll
vargs_align.ll
vargs.ll
vbits.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
vbsl-constant.ll
vbsl.ll
vceq.ll
vcge.ll
vcgt.ll
vcmp-crash.ll
vcnt.ll
vcombine.ll	[SchedModel] Fix for read advance cycles with implicit pseudo operands.	2018-10-30 15:04:40 +00:00
vcvt_combine.ll	[CodeGen] Always use printReg to print registers in both MIR and debug	2017-11-30 16:12:24 +00:00
vcvt-cost.ll
vcvt-v8.ll
vcvt.ll	[LegalizeVectorTypes][X86][ARM][AArch64][PowerPC] Don't use SplitVecOp_TruncateHelper for FP_TO_SINT/UINT.	2018-11-26 21:12:39 +00:00
vdiv_combine.ll	[CodeGen] Always use printReg to print registers in both MIR and debug	2017-11-30 16:12:24 +00:00
vdup.ll	[DAGCombiner] Remove reduceBuildVecConvertToConvertBuildVec and rely on the vectorizers instead (PR35732)	2018-11-02 11:06:18 +00:00
vector-DAGCombine.ll	[LegalizeVectorTypes] Don't use SplitVecOp_TruncateHelper if we're heading towards scalarizing the type.	2018-11-23 02:32:13 +00:00
vector-extend-narrow.ll	[ARM][NFC] Make tests immune to better div optimizations	2018-10-30 22:08:13 +00:00
vector-load.ll	[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)	2018-05-01 19:26:15 +00:00
vector-promotion.ll
vector-spilling.ll
vector-store.ll
vext.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
vfcmp.ll	[ARM][NFC] Replaced tab characters in test file vfcmp.ll.	2018-08-07 08:05:15 +00:00
vfloatintrinsics.ll
vfp-libcalls.ll
vfp-reg-stride.ll	[ARM] Replace processor check with feature	2018-08-09 16:13:24 +00:00
vfp-regs-dwarf.ll	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
vfp.ll
vget_lane.ll
vhadd.ll
vhsub.ll
vicmp-64.ll
vicmp.ll
virtregrewriter-subregliveness.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
vld1.ll
vld2.ll
vld3.ll	[ARM] Fix codegen for VLD3/VLD4/VST3/VST4 with WB	2018-03-02 13:02:55 +00:00
vld4.ll	[ARM] Fix codegen for VLD3/VLD4/VST3/VST4 with WB	2018-03-02 13:02:55 +00:00
vld-vst-upgrade.ll
vlddup.ll
vldlane.ll
vldm-liveness.ll
vldm-liveness.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
vldm-sched-a9.ll
vminmax.ll
vminmaxnm-safe.ll
vminmaxnm.ll
vmla.ll
vmls.ll
vmov.ll
vmul.ll
vneg.ll
vpadal.ll
vpadd.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
vpminmax.ll
vqadd.ll
vqdmul.ll
vqshl.ll
vqshrn.ll
vqsub.ll
vrec.ll
vrev.ll
vrint.ll	[NEON] Support intrinsic for scalar and vector versions of the VRINTN instruction	2018-04-13 12:45:12 +00:00
vsel.ll
vselect_imax.ll
vshift.ll
vshiftins.ll
vshl.ll
vshll.ll	[SelectionDAG] Teach simplifyDemandedBits to handle shifts by constant splat vectors	2017-09-25 19:26:08 +00:00
vshrn.ll
vsra.ll
vst1.ll
vst2.ll
vst3.ll	[ARM] Fix codegen for VLD3/VLD4/VST3/VST4 with WB	2018-03-02 13:02:55 +00:00
vst4.ll	[ARM] Fix codegen for VLD3/VLD4/VST3/VST4 with WB	2018-03-02 13:02:55 +00:00
vstlane.ll
vsub.ll
vtbl.ll
vtrn.ll	[ARM][NFC] Replaced tab-characters in test file vtrn.ll	2018-08-08 14:42:11 +00:00
vuzp.ll	[SchedModel] Fix for read advance cycles with implicit pseudo operands.	2018-10-30 15:04:40 +00:00
vzip.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
warn-stack.ll
weak2.ll
weak.ll
wide-compares.ll	[ARM] Fix CPSR liveness in tMOVCCr_pseudo lowering.	2018-11-07 21:08:13 +00:00
widen-vmovs.ll
wrong-t2stmia-size-opt.ll
xray-armv6-attribute-instrumentation.ll
xray-armv7-attribute-instrumentation.ll
xray-tail-call-sled.ll
zero-cycle-zero.ll
zext-logic-shift-load.ll	[DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst))	2018-04-07 23:36:10 +00:00
zextload_demandedbits.ll